From ad6131b1c48bd61e777fe98ac61252b1b97c8640 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 21 Jan 2022 11:46:20 +0100 Subject: [PATCH] Allow unnamed begin/end block with only variable declarations While it is not a particular useful construct it is legal to have a begin/end block with just variable declarations and no statements. E.g. ``` begin int x; end ``` At the moment there is a special rule for completely empty begin/end blocks. Remove that rule and change the statement_or_null_list in the begin/end block parser section to a statement_or_null_list_opt. This way it covers both completely empty blocks as well as blocks with only variable declarations. Note that this already works as expected for named begin/end blocks. Signed-off-by: Lars-Peter Clausen --- parse.y | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/parse.y b/parse.y index 8680fe3e6..7cbd97823 100644 --- a/parse.y +++ b/parse.y @@ -6593,11 +6593,6 @@ statement_item /* This is roughly statement_item in the LRM */ name. These are handled by pushing the scope name, then matching the declarations. The scope is popped at the end of the block. */ - | K_begin K_end - { PBlock*tmp = new PBlock(PBlock::BL_SEQ); - FILE_NAME(tmp, @1); - $$ = tmp; - } /* In SystemVerilog an unnamed block can contain variable declarations. */ | K_begin { PBlock*tmp = pform_push_block_scope(@1, 0, PBlock::BL_SEQ); @@ -6618,7 +6613,7 @@ statement_item /* This is roughly statement_item in the LRM */ delete tmp; } } - statement_or_null_list K_end + statement_or_null_list_opt K_end { PBlock*tmp; if ($3) { pform_pop_scope();