From a49df16d44bf3c6199bcec16434df30fb4d36488 Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Mon, 24 Mar 2003 02:29:04 +0000
Subject: [PATCH]  Give proper basenames to PAD signals.

---
 tgt-fpga/d-virtex2.c | 19 ++++++++++++++++---
 tgt-fpga/edif.c      | 21 +++++++++++++++++++--
 tgt-fpga/edif.h      |  9 ++++++++-
 3 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/tgt-fpga/d-virtex2.c b/tgt-fpga/d-virtex2.c
index 0a6ecd40b..b95299aad 100644
--- a/tgt-fpga/d-virtex2.c
+++ b/tgt-fpga/d-virtex2.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex2.c,v 1.1 2003/03/24 00:47:54 steve Exp $"
+#ident "$Id: d-virtex2.c,v 1.2 2003/03/24 02:29:04 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -263,6 +263,7 @@ static void virtex2_show_header(ivl_design_t des)
       ivl_scope_t root = ivl_design_root(des);
       unsigned sig_cnt = ivl_scope_sigs(root);
       unsigned nports = 0, pidx;
+      const char*part_str = 0;
 
 	/* Count the ports I'm going to use. */
       for (idx = 0 ;  idx < sig_cnt ;  idx += 1) {
@@ -304,8 +305,8 @@ static void virtex2_show_header(ivl_design_t des)
 
       xlib = edif_xlibrary_create(edf, "VIRTEX2");
 
-      if (ivl_design_flag(des, "part")) {
-	    edif_pstring(edf, "PART", ivl_design_flag(des, "part"));
+      if ( (part_str = ivl_design_flag(des, "part")) && (part_str[0] != 0) ) {
+	    edif_pstring(edf, "PART", part_str);
       }
 
       cell_0 = edif_xcell_create(xlib, "GND", 1);
@@ -393,6 +394,13 @@ static void virtex2_pad(ivl_signal_t sig, const char*str)
 	    edif_joint_t jnt;
 	    edif_cellref_t pad, buf;
 
+	    const char*name_str = ivl_signal_basename(sig);
+	    if (ivl_signal_pins(sig) > 1) {
+		  char name_buf[128];
+		  sprintf(name_buf, "%s[%u]", name_str, idx);
+		  name_str = strdup(name_buf);
+	    }
+
 	    switch (ivl_signal_port(sig)) {
 		case IVL_SIP_INPUT:
 		  check_cell_ibuf();
@@ -400,6 +408,7 @@ static void virtex2_pad(ivl_signal_t sig, const char*str)
 		  buf = edif_cellref_create(edf, cell_ibuf);
 
 		  jnt = edif_joint_create(edf);
+		  edif_joint_rename(jnt, name_str);
 		  edif_add_to_joint(jnt, pad, 0);
 		  edif_add_to_joint(jnt, buf, BUF_I);
 
@@ -413,6 +422,7 @@ static void virtex2_pad(ivl_signal_t sig, const char*str)
 		  buf = edif_cellref_create(edf, cell_obuf);
 
 		  jnt = edif_joint_create(edf);
+		  edif_joint_rename(jnt, name_str);
 		  edif_add_to_joint(jnt, pad, 0);
 		  edif_add_to_joint(jnt, buf, BUF_O);
 
@@ -1131,6 +1141,9 @@ const struct device_s d_virtex2_edif = {
 
 /*
  * $Log: d-virtex2.c,v $
+ * Revision 1.2  2003/03/24 02:29:04  steve
+ *  Give proper basenames to PAD signals.
+ *
  * Revision 1.1  2003/03/24 00:47:54  steve
  *  Add new virtex2 architecture family, and
  *  also the new edif.h EDIF management functions.
diff --git a/tgt-fpga/edif.c b/tgt-fpga/edif.c
index 03e48b3ec..8a5f408ed 100644
--- a/tgt-fpga/edif.c
+++ b/tgt-fpga/edif.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: edif.c,v 1.1 2003/03/24 00:47:54 steve Exp $"
+#ident "$Id: edif.c,v 1.2 2003/03/24 02:29:04 steve Exp $"
 #endif
 
 # include  "edif.h"
@@ -89,6 +89,7 @@ struct joint_cell_ {
 };
 
 struct edif_joint_s {
+      const char*name;
       struct joint_cell_*links;
       struct edif_joint_s*next;
 };
@@ -234,6 +235,7 @@ edif_joint_t edif_joint_create(edif_t edf)
 {
       edif_joint_t jnt = malloc(sizeof(struct edif_joint_s));
 
+      jnt->name = 0;
       jnt->links = 0;
       jnt->next  = edf->nexa;
       edf->nexa  = jnt;
@@ -255,6 +257,12 @@ edif_joint_t edif_joint_of_nexus(edif_t edf, ivl_nexus_t nex)
       return jnt;
 }
 
+void edif_joint_rename(edif_joint_t jnt, const char*name)
+{
+      assert(jnt->name == 0);
+      jnt->name = name;
+}
+
 void edif_add_to_joint(edif_joint_t jnt, edif_cellref_t cell, unsigned port)
 {
       struct joint_cell_* jc = malloc(sizeof(struct joint_cell_));
@@ -388,7 +396,13 @@ void edif_print(FILE*fd, edif_t edf)
       idx = 0;
       for (jnt = edf->nexa ;  jnt ;  jnt = jnt->next, idx += 1) {
 	    struct joint_cell_*jc;
-	    fprintf(fd, "(net N%u (joined", idx);
+
+	    fprintf(fd, "(net ");
+	    if (jnt->name != 0)
+		  fprintf(fd, "(rename N%u \"%s\")", idx, jnt->name);
+	    else
+		  fprintf(fd, "N%u", idx);
+	    fprintf(fd, " (joined");
 
 	    for (jc = jnt->links ;  jc ;  jc = jc->next) {
 		  if (jc->cell)
@@ -427,6 +441,9 @@ void edif_print(FILE*fd, edif_t edf)
 
 /*
  * $Log: edif.c,v $
+ * Revision 1.2  2003/03/24 02:29:04  steve
+ *  Give proper basenames to PAD signals.
+ *
  * Revision 1.1  2003/03/24 00:47:54  steve
  *  Add new virtex2 architecture family, and
  *  also the new edif.h EDIF management functions.
diff --git a/tgt-fpga/edif.h b/tgt-fpga/edif.h
index 446b89baa..6a360ceb1 100644
--- a/tgt-fpga/edif.h
+++ b/tgt-fpga/edif.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: edif.h,v 1.1 2003/03/24 00:47:54 steve Exp $"
+#ident "$Id: edif.h,v 1.2 2003/03/24 02:29:04 steve Exp $"
 #endif
 
 # include  <stdio.h>
@@ -180,6 +180,10 @@ extern edif_joint_t edif_joint_of_nexus(edif_t edf, ivl_nexus_t nex);
    anonymous joint. */
 extern edif_joint_t edif_joint_create(edif_t edf);
 
+/* Renaming a joint causes it to take on a name when external tools
+   view the EDIF file. */
+extern void edif_joint_rename(edif_joint_t jnt, const char*name);
+
 /* Given a joint, this function adds the cell reference. */
 extern void edif_add_to_joint(edif_joint_t jnt,
 			      edif_cellref_t cell,
@@ -193,6 +197,9 @@ extern void edif_print(FILE*fd, edif_t design);
 
 /*
  * $Log: edif.h,v $
+ * Revision 1.2  2003/03/24 02:29:04  steve
+ *  Give proper basenames to PAD signals.
+ *
  * Revision 1.1  2003/03/24 00:47:54  steve
  *  Add new virtex2 architecture family, and
  *  also the new edif.h EDIF management functions.