From a14118cd6c9739eea8b9bf3fc2a84f02dadee208 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Sun, 16 May 2021 17:19:13 +0100
Subject: [PATCH] Do not force lossless calculation for index expressions
 (issue #515)

The standard Verilog expression bit length rules must be used.

(cherry picked from commit a040ddc0702b3fcee4b7a9e60c9415024ef3931a)
---
 netmisc.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/netmisc.cc b/netmisc.cc
index 1546030e8..feee9add8 100644
--- a/netmisc.cc
+++ b/netmisc.cc
@@ -543,7 +543,7 @@ void indices_to_expressions(Design*des, NetScope*scope,
 	    }
 	    ivl_assert(*loc, cur->msb);
 
-	    NetExpr*word_index = elab_and_eval_lossless(des, scope, cur->msb, -2, need_const);
+	    NetExpr*word_index = elab_and_eval(des, scope, cur->msb, -1, need_const);
 
 	    if (word_index == 0)
 		  flags.invalid = true;