From 9e9d5ccfdd7046d054323156ac7d11e7e4a437ee Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Fri, 23 Mar 2007 23:02:31 +0000
Subject: [PATCH]  Fix compile time eval of <= comparison.

---
 eval_tree.cc |  9 +++++++--
 verinum.cc   | 17 ++++++++++++++++-
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/eval_tree.cc b/eval_tree.cc
index 670d17940..41526f2ac 100644
--- a/eval_tree.cc
+++ b/eval_tree.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: eval_tree.cc,v 1.62.2.4 2007/03/23 20:59:25 steve Exp $"
+#ident "$Id: eval_tree.cc,v 1.62.2.5 2007/03/23 23:02:31 steve Exp $"
 #endif
 
 # include "config.h"
@@ -367,7 +367,9 @@ NetEConst* NetEBComp::eval_leeq_()
 	   equal to the largest value the left side can possibly
 	   have. */
       assert(left_->expr_width() > 0);
-      verinum lv (verinum::V1, left_->expr_width());
+      verinum lv (verinum::V1, left_->expr_width() + 1);
+      lv.set(left_->expr_width(), verinum::V0);
+      lv.has_sign( left_->has_sign() );
       if (lv <= rv) {
 	    verinum result(verinum::V1, 1);
 	    return new NetEConst(result);
@@ -1551,6 +1553,9 @@ NetEConst* NetEUReduce::eval_tree()
 
 /*
  * $Log: eval_tree.cc,v $
+ * Revision 1.62.2.5  2007/03/23 23:02:31  steve
+ *  Fix compile time eval of <= comparison.
+ *
  * Revision 1.62.2.4  2007/03/23 20:59:25  steve
  *  Fix compile time evaluation of < operator.
  *
diff --git a/verinum.cc b/verinum.cc
index 043010ed5..633d7872f 100644
--- a/verinum.cc
+++ b/verinum.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: verinum.cc,v 1.43.2.3 2007/03/23 20:59:26 steve Exp $"
+#ident "$Id: verinum.cc,v 1.43.2.4 2007/03/23 23:02:31 steve Exp $"
 #endif
 
 # include "config.h"
@@ -488,6 +488,18 @@ verinum::V operator == (const verinum&left, const verinum&right)
 
 verinum::V operator <= (const verinum&left, const verinum&right)
 {
+      if (left.has_sign() && right.has_sign()) {
+	    if (!left.is_defined())
+		  return verinum::Vx;
+	    if (!right.is_defined())
+		  return verinum::Vx;
+	    long diff = left.as_long() - right.as_long();
+	    if (diff <= 0)
+		  return verinum::V1;
+	    else
+		  return verinum::V0;
+      }
+
       unsigned idx;
       for (idx = left.len() ; idx > right.len() ;  idx -= 1) {
 	    if (left[idx-1] != verinum::V0) return verinum::V0;
@@ -986,6 +998,9 @@ verinum::V operator ^ (verinum::V l, verinum::V r)
 
 /*
  * $Log: verinum.cc,v $
+ * Revision 1.43.2.4  2007/03/23 23:02:31  steve
+ *  Fix compile time eval of <= comparison.
+ *
  * Revision 1.43.2.3  2007/03/23 20:59:26  steve
  *  Fix compile time evaluation of < operator.
  *