diff --git a/elab_expr.cc b/elab_expr.cc
index 231791390..765fca14a 100644
--- a/elab_expr.cc
+++ b/elab_expr.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_expr.cc,v 1.44 2001/11/19 01:54:14 steve Exp $"
+#ident "$Id: elab_expr.cc,v 1.45 2001/11/19 02:54:12 steve Exp $"
 #endif
 
 # include "config.h"
@@ -48,7 +48,6 @@ NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope) const
       assert(left_);
       assert(right_);
 
-
       NetExpr*lp = left_->elaborate_expr(des, scope);
       NetExpr*rp = right_->elaborate_expr(des, scope);
       if ((lp == 0) || (rp == 0)) {
@@ -57,6 +56,7 @@ NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope) const
 	    return 0;
       }
 
+
 	/* If either expression can be evaluated ahead of time, then
 	   do so. This can prove helpful later. */
       { NetExpr*tmp;
@@ -65,6 +65,7 @@ NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope) const
 	      delete lp;
 	      lp = tmp;
 	}
+
 	tmp = rp->eval_tree();
 	if (tmp) {
 	      delete rp;
@@ -635,11 +636,16 @@ NetEUnary* PEUnary::elaborate_expr(Design*des, NetScope*scope) const
 	    tmp->set_line(*this);
 	    break;
       }
+
       return tmp;
 }
 
 /*
  * $Log: elab_expr.cc,v $
+ * Revision 1.45  2001/11/19 02:54:12  steve
+ *  Handle division and modulus by zero while
+ *  evaluating run-time constants.
+ *
  * Revision 1.44  2001/11/19 01:54:14  steve
  *  Port close cropping behavior from mcrgb
  *  Move window array reset to libmc.
diff --git a/verinum.cc b/verinum.cc
index e0ae0d5d0..8632ca813 100644
--- a/verinum.cc
+++ b/verinum.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: verinum.cc,v 1.28 2001/11/06 06:11:55 steve Exp $"
+#ident "$Id: verinum.cc,v 1.29 2001/11/19 02:54:12 steve Exp $"
 #endif
 
 # include "config.h"
@@ -655,6 +655,14 @@ verinum operator / (const verinum&left, const verinum&right)
 	    return result;
       }
 
+	/* If the right expression is a zero value, then the result is
+	   filled with 'bx bits. */
+      if (right.as_ulong() == 0) {
+	    verinum result (verinum::Vx, use_len, has_len_flag);
+	    result.has_sign(left.has_sign() || right.has_sign());
+	    return result;
+      }
+
       verinum result(verinum::Vz, use_len, has_len_flag);
       result.has_sign(left.has_sign() || right.has_sign());
 
@@ -707,6 +715,14 @@ verinum operator % (const verinum&left, const verinum&right)
 	    return result;
       }
 
+	/* If the right expression is a zero value, then the result is
+	   filled with 'bx bits. */
+      if (right.as_ulong() == 0) {
+	    verinum result (verinum::Vx, use_len, has_len_flag);
+	    result.has_sign(left.has_sign() || right.has_sign());
+	    return result;
+      }
+
       verinum result(verinum::Vz, use_len, has_len_flag);
       result.has_sign(left.has_sign() || right.has_sign());
 
@@ -770,6 +786,10 @@ verinum::V operator & (verinum::V l, verinum::V r)
 
 /*
  * $Log: verinum.cc,v $
+ * Revision 1.29  2001/11/19 02:54:12  steve
+ *  Handle division and modulus by zero while
+ *  evaluating run-time constants.
+ *
  * Revision 1.28  2001/11/06 06:11:55  steve
  *  Support more real arithmetic in delay constants.
  *