diff --git a/elab_net.cc b/elab_net.cc
index 510f78a1d..5fb9f706f 100644
--- a/elab_net.cc
+++ b/elab_net.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1999-2009 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1999-2011 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -84,12 +84,7 @@ NetNet* PEConcat::elaborate_lnet_common_(Design*des, NetScope*scope,
 
       }
 
-	/* If any of the sub expressions failed to elaborate, then
-	   delete all those that did and abort myself. */
       if (errors) {
-	    for (unsigned idx = 0 ;  idx < nets.count() ;  idx += 1) {
-		  if (nets[idx]) delete nets[idx];
-	    }
 	    des->errors += errors;
 	    return 0;
       }
diff --git a/elaborate.cc b/elaborate.cc
index 19d339c85..738ecd51f 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2010 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 1998-2011 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -1326,8 +1326,9 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 			     << "Inout port expression must support "
 			     << "continuous assignment." << endl;
 			cerr << pins[idx]->get_fileline() << ":      : "
-			     << "Port of " << rmod->mod_name()
-			     << " is " << rmod->ports[idx]->name << endl;
+			     << "Port " << rmod->ports[idx]->name << " of "
+			     << rmod->mod_name() << " is connected to "
+			     << *pins[idx] << endl;
 			des->errors += 1;
 			continue;
 		  }
@@ -1372,8 +1373,9 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 			     << "Output port expression must support "
 			     << "continuous assignment." << endl;
 			cerr << pins[idx]->get_fileline() << ":      : "
-			     << "Port of " << rmod->mod_name()
-			     << " is " << rmod->ports[idx]->name << endl;
+			     << "Port " << rmod->ports[idx]->name << " of "
+			     << rmod->mod_name() << " is connected to "
+			     << *pins[idx] << endl;
 			des->errors += 1;
 			continue;
 		  }