diff --git a/elaborate.cc b/elaborate.cc
index 3010ae2db..86e48a388 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -1538,7 +1538,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 		    // array, then there should be no sub-ports and
 		    // the r-value expression is processed
 		    // differently.
-		  if (prts.size() >= 1 && prts[0]->pin_count()>1) {
+		  if (prts.size() >= 1 && prts[0]->unpacked_dimensions() > 0) {
 			ivl_assert(*this, prts.size()==1);
 			elaborate_unpacked_port(des, scope, prts[0], pins[idx],
 						ptype, rmod, idx);
@@ -1703,7 +1703,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 		    // differently. Note that we are calling it the
 		    // "r-value" expression, but since this is an
 		    // output port, we assign to it from the internal object.
-		  if (prts[0]->pin_count() > 1) {
+		  if (prts[0]->unpacked_dimensions() > 0) {
 			elaborate_unpacked_port(des, scope, prts[0], pins[idx],
 						ptype, rmod, idx);
 			continue;
diff --git a/ivtest/ivltests/module_port_array1.v b/ivtest/ivltests/module_port_array1.v
new file mode 100644
index 000000000..0e15966cb
--- /dev/null
+++ b/ivtest/ivltests/module_port_array1.v
@@ -0,0 +1,32 @@
+// Check that connecting a module port array with a single element is supported
+
+module M (
+  input [7:0] in[0:0],
+  output [7:0] out[0:0]
+);
+
+  assign out[0] = in[0];
+
+endmodule
+
+module test;
+
+  reg [7:0] A[0:0];
+  wire [7:0] B[0:0];
+
+  M i_m (
+    .in(A),
+    .out(B)
+  );
+
+  initial begin
+    A[0] = 10;
+    #1
+    if (B[0] === 10) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule
diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list
index 8b0ce376c..c247768e5 100644
--- a/ivtest/regress-vvp.list
+++ b/ivtest/regress-vvp.list
@@ -26,6 +26,7 @@ dumpfile			vvp_tests/dumpfile.json
 final3				vvp_tests/final3.json
 macro_str_esc			vvp_tests/macro_str_esc.json
 memsynth1			vvp_tests/memsynth1.json
+module_port_array1		vvp_tests/module_port_array1.json
 param-width			vvp_tests/param-width.json
 param-width-vlog95		vvp_tests/param-width-vlog95.json
 pr1388974			vvp_tests/pr1388974.json
diff --git a/ivtest/vvp_tests/module_port_array1.json b/ivtest/vvp_tests/module_port_array1.json
new file mode 100644
index 000000000..8aed8457c
--- /dev/null
+++ b/ivtest/vvp_tests/module_port_array1.json
@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "module_port_array1.v",
+    "iverilog-args" : [ "-g2009" ]
+}