From 9b68c5776ba311407708598326daa6b3e5e11de2 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 17 Sep 2022 22:01:58 +0200 Subject: [PATCH] Allow objects to be assigned to a variable of a base class SystemVerilog allows objects to be assigned to a variable that is a base type of the objects type. E.g. ``` class B; endclass Class C extends B; endclass C c = new B b = c; ``` Add a type_compatibility() method for netclass_t that allows these kinds of assignments. This already works fine in vvp since, as SystemVerilog does not support multiple inheritance, properties will always be at the same offset in the base class and the inheriting class. Signed-off-by: Lars-Peter Clausen --- netclass.cc | 11 +++++++++++ netclass.h | 3 +++ 2 files changed, 14 insertions(+) diff --git a/netclass.cc b/netclass.cc index 3365a8949..99ad5d68a 100644 --- a/netclass.cc +++ b/netclass.cc @@ -195,3 +195,14 @@ const NetExpr* netclass_t::get_parameter(Design *des, perm_string name, { return class_scope_->get_parameter(des, name, par_type); } + +bool netclass_t::test_compatibility(ivl_type_t that) const +{ + for (const netclass_t *class_type = dynamic_cast(that); + class_type; class_type = class_type->get_super()) { + if (class_type == this) + return true; + } + + return false; +} diff --git a/netclass.h b/netclass.h index 0c598fe32..a34487e9b 100644 --- a/netclass.h +++ b/netclass.h @@ -119,6 +119,9 @@ class netclass_t : public ivl_type_s { void set_virtual(bool virtual_class) { virtual_class_ = virtual_class; } bool is_virtual() const { return virtual_class_; } + protected: + bool test_compatibility(ivl_type_t that) const; + private: perm_string name_; // If this is derived from another base class, point to it