From 9b3c3b6e7a56d3a201f62889f1fa29edf1608ca1 Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Fri, 21 Jan 2000 05:41:51 +0000
Subject: [PATCH]  add the -m flag.

---
 verilog.1  | 2 ++
 verilog.sh | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/verilog.1 b/verilog.1
index ad9d4a410..83addb2ec 100644
--- a/verilog.1
+++ b/verilog.1
@@ -31,6 +31,8 @@ Defines macro \fImacro\fP as \fIdefn\fP.
 .B -I\fIincludepath\fP 
 Append path \fIincludepath\fP to list of paths searched for include files.
 .TP 8
+.B -m\fImodule\fP
+Add this module to the list of modules to be loaded by the simulation.
 .B -X
 Generate XNF files as output. Default is VVM-format.
 .TP 8
diff --git a/verilog.sh b/verilog.sh
index d6b387c6b..ad37a093f 100644
--- a/verilog.sh
+++ b/verilog.sh
@@ -46,7 +46,7 @@ flags=""
 #fi
 
 # Try to extract given parameters
-parameter=`getopt D:I:Xxf:o:s:t: "$@"` 
+parameter=`getopt D:I:Xxf:m:o:s:t: "$@"` 
 eval set -- "${parameter}" 
 while true ; do 
 
@@ -55,6 +55,7 @@ while true ; do
       -I) extIncPath="${extIncPath} -I $2" ; shift 2 ;;
       -X) target="xnf" ; shift ;;
       -f) flags="$flags -f$2" ; shift 2 ;;
+      -m) flags="$flags -m$2" ; shift 2 ;;
       -o) outputFile=$2 ; shift 2 ;;
       -s) topModule="-s $2 " ; shift 2 ;;
       -t) target="$2" ; shift 2 ;;