From 97e31ec9fac70608c4ae9b8ec3453e722626f589 Mon Sep 17 00:00:00 2001
From: Maciej Suminski <maciej.suminski@cern.ch>
Date: Tue, 15 Mar 2016 16:03:56 +0100
Subject: [PATCH] vhdlpp: Workaround to make subprograms work as if they were
 automatic.

---
 vhdlpp/subprogram_emit.cc | 18 +++++++++++++++---
 vhdlpp/vsignal.cc         |  4 ++--
 vhdlpp/vsignal.h          |  3 +--
 3 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/vhdlpp/subprogram_emit.cc b/vhdlpp/subprogram_emit.cc
index af25ea3bf..0b6f27f11 100644
--- a/vhdlpp/subprogram_emit.cc
+++ b/vhdlpp/subprogram_emit.cc
@@ -32,9 +32,21 @@ int SubprogramBody::emit_package(ostream&fd) const
 
       for (map<perm_string,Variable*>::const_iterator cur = new_variables_.begin()
          ; cur != new_variables_.end() ; ++cur) {
-        // Enable reg_flag for variables
-        cur->second->count_ref_sequ();
-        errors += cur->second->emit(fd, NULL, NULL);
+          // Enable reg_flag for variables
+          cur->second->count_ref_sequ();
+          errors += cur->second->emit(fd, NULL, NULL);
+      }
+
+    // Emulate automatic functions (add explicit initial value assignments)
+      for (map<perm_string,Variable*>::const_iterator cur = new_variables_.begin()
+         ; cur != new_variables_.end() ; ++cur) {
+          Variable*var = cur->second;
+
+          if(const Expression*init = var->peek_init_expr()) {
+              fd << cur->first << " = ";
+              init->emit(fd, NULL, NULL);
+              fd << "; -- automatic function emulation" << endl;
+          }
       }
 
       if (statements_) {
diff --git a/vhdlpp/vsignal.cc b/vhdlpp/vsignal.cc
index ab949d7e1..8576c212e 100644
--- a/vhdlpp/vsignal.cc
+++ b/vhdlpp/vsignal.cc
@@ -62,7 +62,7 @@ int Signal::emit(ostream&out, Entity*ent, ScopeBase*scope)
 	    decl.reg_flag = true;
       errors += decl.emit(out, peek_name());
 
-      Expression*init_expr = peek_init_expr();
+      const Expression*init_expr = peek_init_expr();
       if (init_expr) {
             /* Emit initialization value for wires as a weak assignment */
             if(!decl.reg_flag && !type->type_match(&primitive_REAL))
@@ -84,7 +84,7 @@ int Variable::emit(ostream&out, Entity*ent, ScopeBase*scope)
       decl.reg_flag = true;
       errors += decl.emit(out, peek_name());
 
-      Expression*init_expr = peek_init_expr();
+      const Expression*init_expr = peek_init_expr();
       if (init_expr) {
 	    out << " = ";
 	    init_expr->emit(out, ent, scope);
diff --git a/vhdlpp/vsignal.h b/vhdlpp/vsignal.h
index 9beda6cef..e387d8954 100644
--- a/vhdlpp/vsignal.h
+++ b/vhdlpp/vsignal.h
@@ -46,14 +46,13 @@ class SigVarBase : public LineInfo {
       void elaborate(Entity*ent, ScopeBase*scope);
 
       perm_string peek_name() const { return name_; }
+      const Expression* peek_init_expr() const { return init_expr_; }
 
     protected:
       unsigned peek_refcnt_sequ_() const { return refcnt_sequ_; }
 
       void type_elaborate_(VType::decl_t&decl);
 
-      Expression* peek_init_expr() const { return init_expr_; }
-
     private:
       perm_string name_;
       const VType*type_;