From 957a4647435c180dd176ee29904ebd7ac7830132 Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Wed, 25 Jun 2003 01:46:44 +0000
Subject: [PATCH]  Virtex support for NOT gates.

---
 tgt-fpga/d-virtex2.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/tgt-fpga/d-virtex2.c b/tgt-fpga/d-virtex2.c
index 2aa66d58b..1ff4018bf 100644
--- a/tgt-fpga/d-virtex2.c
+++ b/tgt-fpga/d-virtex2.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex2.c,v 1.11 2003/06/24 03:55:00 steve Exp $"
+#ident "$Id: d-virtex2.c,v 1.12 2003/06/25 01:46:44 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -409,6 +409,18 @@ static void virtex2_logic(ivl_net_logic_t net)
 	    edif_add_to_joint(jnt, obj, BUF_I);
 	    break;
 
+	  case IVL_LO_NOT:
+	    assert(ivl_logic_pins(net) == 2);
+
+	    obj = edif_cellref_create(edf, xilinx_cell_inv(xlib));
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
+	    edif_add_to_joint(jnt, obj, BUF_O);
+
+	    jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
+	    edif_add_to_joint(jnt, obj, BUF_I);
+	    break;
+
 	  case IVL_LO_AND:
 	    assert(ivl_logic_pins(net) <= 5);
 	    assert(ivl_logic_pins(net) >= 3);
@@ -1127,6 +1139,9 @@ const struct device_s d_virtex2_edif = {
 
 /*
  * $Log: d-virtex2.c,v $
+ * Revision 1.12  2003/06/25 01:46:44  steve
+ *  Virtex support for NOT gates.
+ *
  * Revision 1.11  2003/06/24 03:55:00  steve
  *  Add ivl_synthesis_cell support for virtex2.
  *