diff --git a/vhdlpp/entity_elaborate.cc b/vhdlpp/entity_elaborate.cc index b1858776b..8ae49c73c 100644 --- a/vhdlpp/entity_elaborate.cc +++ b/vhdlpp/entity_elaborate.cc @@ -139,6 +139,7 @@ int Entity::elaborate_ports_(void) cur_decl.msb = arr_type->dimension(0).msb(); cur_decl.lsb = arr_type->dimension(0).lsb(); + cur_decl.signed_flag = arr_type->signed_vector(); } else { cerr << get_fileline() << ": error: " diff --git a/vhdlpp/entity_emit.cc b/vhdlpp/entity_emit.cc index 21d711328..1302f5da9 100644 --- a/vhdlpp/entity_emit.cc +++ b/vhdlpp/entity_emit.cc @@ -88,6 +88,8 @@ int Entity::emit(ostream&out) break; case VLOGIC: out << "wire logic "; + if (cur->second.signed_flag) + out << "signed "; if (cur->second.msb != cur->second.lsb) out << "[" << cur->second.msb << ":" << cur->second.lsb << "] "; diff --git a/vhdlpp/parse_misc.cc b/vhdlpp/parse_misc.cc index 31bc90252..2bd78e6e5 100644 --- a/vhdlpp/parse_misc.cc +++ b/vhdlpp/parse_misc.cc @@ -81,7 +81,7 @@ const VType* calculate_subtype(const char*base_name, range[0] = VTypeArray::range_t(left_val, right_val); - VTypeArray*subtype = new VTypeArray(base_array->element_type(), range); + VTypeArray*subtype = new VTypeArray(base_array->element_type(), range, base_array->signed_vector()); return subtype; } diff --git a/vhdlpp/vtype.cc b/vhdlpp/vtype.cc index 33e4baa59..82c99e96f 100644 --- a/vhdlpp/vtype.cc +++ b/vhdlpp/vtype.cc @@ -29,12 +29,16 @@ const VTypePrimitive primitive_BIT (VTypePrimitive::BIT);; const VTypePrimitive primitive_INTEGER (VTypePrimitive::INTEGER);; const VTypePrimitive primitive_STDLOGIC(VTypePrimitive::STDLOGIC);; +const VTypeArray primitive_BIT_VECTOR(&primitive_BIT, vector (1)); +const VTypeArray primitive_BOOL_VECTOR(&primitive_BOOLEAN, vector (1)); + void preload_global_types(void) { global_types[perm_string::literal("boolean")] = &primitive_BOOLEAN; global_types[perm_string::literal("bit")] = &primitive_BIT; global_types[perm_string::literal("integer")] = &primitive_INTEGER; global_types[perm_string::literal("std_logic")] = &primitive_STDLOGIC; + global_types[perm_string::literal("bit_vector")]= &primitive_BOOL_VECTOR; } void import_ieee(void) @@ -51,11 +55,11 @@ static void import_ieee_use_numeric_bit(perm_string name) if (all_flag || name == "signed") { vector dims (1); - global_types[perm_string::literal("signed")] = new VTypeArray(&primitive_STDLOGIC, dims); + global_types[perm_string::literal("signed")] = new VTypeArray(&primitive_STDLOGIC, dims, true); } if (all_flag || name == "unsigned") { vector dims (1); - global_types[perm_string::literal("unsigned")] = new VTypeArray(&primitive_BIT, dims); + global_types[perm_string::literal("unsigned")] = new VTypeArray(&primitive_BIT, dims, false); } } @@ -127,8 +131,8 @@ void VTypePrimitive::show(ostream&out) const } } -VTypeArray::VTypeArray(const VType*element, const vector&r) -: etype_(element), ranges_(r) +VTypeArray::VTypeArray(const VType*element, const vector&r, bool sv) +: etype_(element), ranges_(r), signed_flag_(sv) { } @@ -154,6 +158,8 @@ void VTypeArray::show(ostream&out) const out << "(" << cur->msb() << " downto " << cur->lsb() << ")"; } out << " of "; + if (signed_flag_) + out << "signed "; if (etype_) etype_->show(out); else diff --git a/vhdlpp/vtype.h b/vhdlpp/vtype.h index c22b413d4..4a2984785 100644 --- a/vhdlpp/vtype.h +++ b/vhdlpp/vtype.h @@ -108,7 +108,7 @@ class VTypeArray : public VType { }; public: - VTypeArray(const VType*etype, const std::vector&r); + VTypeArray(const VType*etype, const std::vector&r, bool signed_vector =false); ~VTypeArray(); void show(std::ostream&) const; @@ -117,12 +117,15 @@ class VTypeArray : public VType { const range_t&dimension(size_t idx) const { return ranges_[idx]; } + bool signed_vector() const { return signed_flag_; } + const VType* element_type() const; private: const VType*etype_; std::vector ranges_; + bool signed_flag_; }; #endif