From 8df804c273c7f9620cb7f022b000b1c36c98c6bd Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 26 Jul 2026 12:25:29 -0700 Subject: [PATCH] Add regression tests for wildcard port declaration order Check separately that a wildcard port connection ignores a declaration after the module instance in strict mode and uses the port default. Check the exact position of `.*`: an implicit net created by an explicit connection before `.*` is connected, while one created after `.*` is not. Check that `-gno-strict-net-var-declaration` preserves relaxed behavior and binds a declaration introduced after `.*`. Run all three tests through the native and vlog95 backends. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/sv_wildcard_port_order.v | 25 +++++++++ .../ivltests/sv_wildcard_port_order_relaxed.v | 29 ++++++++++ ivtest/ivltests/sv_wildcard_port_position.v | 55 +++++++++++++++++++ ivtest/regress-vvp.list | 3 + ivtest/vvp_tests/sv_wildcard_port_order.json | 5 ++ .../sv_wildcard_port_order_relaxed.json | 6 ++ .../vvp_tests/sv_wildcard_port_position.json | 5 ++ 7 files changed, 128 insertions(+) create mode 100644 ivtest/ivltests/sv_wildcard_port_order.v create mode 100644 ivtest/ivltests/sv_wildcard_port_order_relaxed.v create mode 100644 ivtest/ivltests/sv_wildcard_port_position.v create mode 100644 ivtest/vvp_tests/sv_wildcard_port_order.json create mode 100644 ivtest/vvp_tests/sv_wildcard_port_order_relaxed.json create mode 100644 ivtest/vvp_tests/sv_wildcard_port_position.json diff --git a/ivtest/ivltests/sv_wildcard_port_order.v b/ivtest/ivltests/sv_wildcard_port_order.v new file mode 100644 index 000000000..48fca1be1 --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_port_order.v @@ -0,0 +1,25 @@ +// Check that wildcard port connections ignore later declarations. + +module child(input wire value = 1'b0, output wire result); + + assign result = value; + +endmodule + +module test; + + wire result; + child i_child(.result(result), .*); + wire value = 1'b1; + + initial begin + #1; + + if (result !== 1'b0) begin + $display("FAILED: expected 0, got %b", result); + end else begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_port_order_relaxed.v b/ivtest/ivltests/sv_wildcard_port_order_relaxed.v new file mode 100644 index 000000000..585feda5c --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_port_order_relaxed.v @@ -0,0 +1,29 @@ +// Check relaxed declaration ordering for wildcard port connections. +// This is not valid in strict Verilog and tests +// -gno-strict-net-var-declaration. + +module child(input wire source = 1'b0, input wire value = 1'b0, + output wire result); + + assign result = value; + +endmodule + +module test; + + wire result; + child i_child(.result(result), .*, .source(value)); + + assign value = 1'b1; + + initial begin + #1; + + if (result !== 1'b1) begin + $display("FAILED: expected 1, got %b", result); + end else begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/sv_wildcard_port_position.v b/ivtest/ivltests/sv_wildcard_port_position.v new file mode 100644 index 000000000..7e569493b --- /dev/null +++ b/ivtest/ivltests/sv_wildcard_port_position.v @@ -0,0 +1,55 @@ +// Check that wildcard port connections use the position of `.*`. + +module child(input wire source = 1'b0, input wire value = 1'b0, + output wire result); + + assign result = value; + +endmodule + +module implicit_before(output wire result); + + child i_child(.source(value), .result(result), .*); + + assign value = 1'b1; + +endmodule + +module implicit_after(output wire result); + + child i_child(.result(result), .*, .source(value)); + + assign value = 1'b1; + +endmodule + +module test; + + wire result_before; + wire result_after; + + implicit_before i_before(result_before); + implicit_after i_after(result_after); + + reg failed; + + `define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \ + `"val`", exp, val); \ + failed = 1'b1; \ + end + + initial begin + failed = 1'b0; + #1; + + `check(result_before, 1'b1); + `check(result_after, 1'b0); + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 46f62b1aa..4a871549d 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -494,6 +494,9 @@ sv_type_param_restrict_union2 vvp_tests/sv_type_param_restrict_union2.json sv_type_param_restrict_union_fail1 vvp_tests/sv_type_param_restrict_union_fail1.json sv_type_param_restrict_union_fail2 vvp_tests/sv_type_param_restrict_union_fail2.json sv_wildcard_import8 vvp_tests/sv_wildcard_import8.json +sv_wildcard_port_order vvp_tests/sv_wildcard_port_order.json +sv_wildcard_port_order_relaxed vvp_tests/sv_wildcard_port_order_relaxed.json +sv_wildcard_port_position vvp_tests/sv_wildcard_port_position.json sdf_header vvp_tests/sdf_header.json task_return1 vvp_tests/task_return1.json task_return2 vvp_tests/task_return2.json diff --git a/ivtest/vvp_tests/sv_wildcard_port_order.json b/ivtest/vvp_tests/sv_wildcard_port_order.json new file mode 100644 index 000000000..30128186a --- /dev/null +++ b/ivtest/vvp_tests/sv_wildcard_port_order.json @@ -0,0 +1,5 @@ +{ + "type" : "normal", + "source" : "sv_wildcard_port_order.v", + "iverilog-args" : [ "-g2005-sv" ] +} diff --git a/ivtest/vvp_tests/sv_wildcard_port_order_relaxed.json b/ivtest/vvp_tests/sv_wildcard_port_order_relaxed.json new file mode 100644 index 000000000..c30493244 --- /dev/null +++ b/ivtest/vvp_tests/sv_wildcard_port_order_relaxed.json @@ -0,0 +1,6 @@ +{ + "type" : "normal", + "source" : "sv_wildcard_port_order_relaxed.v", + "iverilog-args" : [ "-g2005-sv", "-gno-strict-net-var-declaration", + "-Wno-declaration-after-use" ] +} diff --git a/ivtest/vvp_tests/sv_wildcard_port_position.json b/ivtest/vvp_tests/sv_wildcard_port_position.json new file mode 100644 index 000000000..823340895 --- /dev/null +++ b/ivtest/vvp_tests/sv_wildcard_port_position.json @@ -0,0 +1,5 @@ +{ + "type" : "normal", + "source" : "sv_wildcard_port_position.v", + "iverilog-args" : [ "-g2005-sv" ] +}