diff --git a/vvp/README.txt b/vvp/README.txt
index 3b56ac40d..344bec160 100644
--- a/vvp/README.txt
+++ b/vvp/README.txt
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
  *
- *  $Id: README.txt,v 1.72 2005/10/12 17:23:15 steve Exp $
+ *  $Id: README.txt,v 1.73 2005/11/10 13:25:31 steve Exp $
  */
 
 VVP SIMULATION ENGINE
@@ -150,6 +150,14 @@ Almost all of the structural aspects of a simulation can be
 represented by functors, which perform the very basic task of
 combining up to four inputs down to one output.
 
+- MUXZ
+
+     Q | A  B  S  n/a
+     --+-------------
+     A | *  *  0
+     B | *  *  1
+
+
 DFF STATEMENTS:
 
 The Verilog language itself does not have a DFF primitive, but post