From 864a86f7ee86740eee2b69f3d9ab580f7661f21a Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Sat, 11 Oct 2008 21:08:14 -0700 Subject: [PATCH] Multiply nodes are always unsigned. It is up to the elaborator to sign-extend the inputs if the multiply is signed in the Verilog source. The run time always processes the multiply as unsigned. --- ivl_target.h | 5 +++-- vvp/arith.cc | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/ivl_target.h b/ivl_target.h index 33b2adb5f..bc5498a52 100644 --- a/ivl_target.h +++ b/ivl_target.h @@ -992,8 +992,9 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net); * more than the width of the output, although the possibility of * overflow exists at run time. * - * Multiply may be signed. If so, the output should be sign extended - * to fill in its result. + * The inputs are always treated as unsigned. If the expression is + * supposed to be signed, elaboration will generate the necessary sign + * extension, so the target need not (must not) consider signedness. * * - Power (IVL_LPM_POW) * The power takes two inputs and generates an output. Unlike other diff --git a/vvp/arith.cc b/vvp/arith.cc index 9a2061504..126cfdaa1 100644 --- a/vvp/arith.cc +++ b/vvp/arith.cc @@ -336,13 +336,13 @@ void vvp_arith_mult::recv_vec4(vvp_net_ptr_t ptr, const vvp_vector4_t&bit) } long a; - if (! vector4_to_value(op_a_, a, true, true)) { + if (! vector4_to_value(op_a_, a, false, true)) { vvp_send_vec4(ptr.ptr()->out, x_val_); return; } long b; - if (! vector4_to_value(op_b_, b, true, true)) { + if (! vector4_to_value(op_b_, b, false, true)) { vvp_send_vec4(ptr.ptr()->out, x_val_); return; }