From 854422a3eb578ee46c680d3d8764af9c1f06fb91 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 19 Apr 2022 11:45:54 +0200 Subject: [PATCH] Allow `shortreal` module ports Currently there is a restriction in the parser that rejects `shortreal` typed module ports. And while at the moment `shortreal` signals are implemented as `real` typed signals, which is not standard compliant, there is nothing special about module ports in this regard. Note that support for `shortreal` (and `real`) nets is an Icarus extension, but ports can also be variables, in which case a shortreal port is allowed by the LRM. `shortreal` variables and nets are allowed everywhere else. There is no good reason to not allow them for module ports, so remove the restriction. Signed-off-by: Lars-Peter Clausen --- pform.cc | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/pform.cc b/pform.cc index 5259b0ac8..18ad80a62 100644 --- a/pform.cc +++ b/pform.cc @@ -2574,16 +2574,10 @@ void pform_module_define_port(const struct vlltype&li, signed_flag = vec_type->signed_flag; prange = vec_type->pdims.get(); vtype = 0; - } else if (real_type_t*rtype = dynamic_cast(vtype)) { + } else if (dynamic_cast(vtype)) { data_type = IVL_VT_REAL; signed_flag = true; prange = 0; - - if (rtype->type_code() != real_type_t::REAL) { - VLerror(li, "sorry: Only real (not shortreal) supported here (%s:%d).", - __FILE__, __LINE__); - } - } else if (vtype) { if (vtype->figure_packed_base_type() != IVL_VT_NO_TYPE) { data_type = vtype->figure_packed_base_type();