diff --git a/ivtest/ivltests/module_port_array_fail1.v b/ivtest/ivltests/module_port_array_fail1.v
new file mode 100644
index 000000000..4d6483ec0
--- /dev/null
+++ b/ivtest/ivltests/module_port_array_fail1.v
@@ -0,0 +1,17 @@
+// Check that an output array port expression must be assignable.
+
+module M (
+  output int out [0:1]
+);
+
+  initial begin
+    out = '{3, 4};
+  end
+
+endmodule
+
+module test;
+
+  M i_m('{1, 2}); // Error: output expression is not assignable
+
+endmodule
diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list
index 0e71d0d6c..c4f96dfa7 100644
--- a/ivtest/regress-vvp.list
+++ b/ivtest/regress-vvp.list
@@ -152,6 +152,7 @@ mix_reset-synth			vvp_tests/mix_reset-synth.json
 module_ordered_list1		vvp_tests/module_ordered_list1.json
 module_ordered_list2		vvp_tests/module_ordered_list2.json
 module_port_array1		vvp_tests/module_port_array1.json
+module_port_array_fail1		vvp_tests/module_port_array_fail1.json
 module_port_array_init1		vvp_tests/module_port_array_init1.json
 monitor4			vvp_tests/monitor4.json
 non-polymorphic-abs		vvp_tests/non-polymorphic-abs.json
diff --git a/ivtest/vvp_tests/module_port_array_fail1.json b/ivtest/vvp_tests/module_port_array_fail1.json
new file mode 100644
index 000000000..a7a343dca
--- /dev/null
+++ b/ivtest/vvp_tests/module_port_array_fail1.json
@@ -0,0 +1,5 @@
+{
+    "type"          : "CE",
+    "source"        : "module_port_array_fail1.v",
+    "iverilog-args" : [ "-g2009" ]
+}