From 7f955cc07040e5dccdf8a3c7177309c1420a69bd Mon Sep 17 00:00:00 2001
From: Nick Gasson <nick@nickg.me.uk>
Date: Mon, 7 Jul 2008 15:36:13 +0100
Subject: [PATCH] Move the VHDL support package

---
 tgt-vhdl/verilog_support.vhd      | 41 +++++++++++++++++++++++++++++++
 tgt-vhdl/vhpi/verilog_support.vhd | 15 -----------
 2 files changed, 41 insertions(+), 15 deletions(-)
 create mode 100644 tgt-vhdl/verilog_support.vhd
 delete mode 100644 tgt-vhdl/vhpi/verilog_support.vhd

diff --git a/tgt-vhdl/verilog_support.vhd b/tgt-vhdl/verilog_support.vhd
new file mode 100644
index 000000000..253d9c21a
--- /dev/null
+++ b/tgt-vhdl/verilog_support.vhd
@@ -0,0 +1,41 @@
+--
+-- Support routines for Icarus Verilog VHDL output
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package Verilog_Support is
+
+  -- This routine implements $finish by terminating the simulation
+  -- It is implemented via the VHPI interface
+  procedure finish;
+  attribute foreign of finish : procedure is "VHPIDIRECT finish";
+
+  -- Routines to implement Verilog reduction operators
+  function Reduce_OR(X : unsigned) return std_logic;
+  
+  
+end Verilog_Support;
+
+package body Verilog_Support is
+
+  -- This is a dummy body to provide a default implementation
+  -- if VHPI is not supported
+  procedure finish is
+  begin
+    assert false severity failure;
+  end finish;
+
+  function Reduce_OR(X : unsigned) return std_logic is
+  begin
+    for I in X'range loop
+      if X(I) /= '1' then
+        return '0';
+      end if;
+    end loop;
+    return '1';
+  end function;  
+  
+end Verilog_Support;
diff --git a/tgt-vhdl/vhpi/verilog_support.vhd b/tgt-vhdl/vhpi/verilog_support.vhd
deleted file mode 100644
index eb77c4c06..000000000
--- a/tgt-vhdl/vhpi/verilog_support.vhd
+++ /dev/null
@@ -1,15 +0,0 @@
---
--- VHPI support routines for VHDL output.
---
-
-package Verilog_Support is
-  procedure finish;
-  attribute foreign of finish : procedure is "VHPIDIRECT finish";
-end Verilog_Support;
-
-package body Verilog_Support is
-  procedure finish is
-  begin
-    assert false severity failure;
-  end finish;
-end Verilog_Support;