From 7aabcc113ed4a7d6c52b24d43fb182e9756c601c Mon Sep 17 00:00:00 2001
From: mole99 <leomoser99@gmail.com>
Date: Wed, 5 Jul 2023 16:24:04 +0200
Subject: [PATCH] Add test for delayed signals in timing checks

---
 .../ivltests/timing_check_delayed_signals.v   | 39 +++++++++++++++++++
 ivtest/regress-vvp.list                       |  2 +
 .../timing_check_delayed_signals.json         |  4 ++
 3 files changed, 45 insertions(+)
 create mode 100644 ivtest/ivltests/timing_check_delayed_signals.v
 create mode 100644 ivtest/vvp_tests/timing_check_delayed_signals.json

diff --git a/ivtest/ivltests/timing_check_delayed_signals.v b/ivtest/ivltests/timing_check_delayed_signals.v
new file mode 100644
index 000000000..9c0542ce6
--- /dev/null
+++ b/ivtest/ivltests/timing_check_delayed_signals.v
@@ -0,0 +1,39 @@
+// Check that when timing checks are disabled (or in the case of Icarus Verilog not supported)
+// that the delayed reference and data signals become copies of the original reference and data signals
+
+module test;
+
+  wire sig1, sig2, del_sig1, del_sig2, del_sig3, del_sig4, notifier, cond1, cond2;
+
+  assign sig1 = 1'b0;
+  assign sig2 = 1'b1;
+
+  specify
+
+    $setuphold(posedge sig1, negedge sig2 , 0:0:0 , 0:0:0 , notifier , cond1 , cond2 , del_sig1 , del_sig2 ) ;
+
+    /*
+    Internally the simulator does the following:
+    assign del_sig1 = sig1;
+    assign del_sig2 = sig2;
+    */
+
+    $recrem(posedge sig1, negedge sig2 , 0:0:0 , 0:0:0 , notifier, cond1 , cond2 , del_sig3 , del_sig4 );
+
+    /*
+    Internally the simulator does the following:
+    assign del_sig3 = sig1;
+    assign del_sig4 = sig2;
+    */
+
+  endspecify
+  
+  initial begin
+  
+      if (del_sig1 == 1'b0 && del_sig2 == 1'b1 && del_sig3 == 1'b0 && del_sig4 == 1'b1)
+        $display("PASSED");
+      else
+        $display("FAILED");
+  end
+
+endmodule
diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list
index fdacfbc4d..05fd8b6d4 100644
--- a/ivtest/regress-vvp.list
+++ b/ivtest/regress-vvp.list
@@ -72,3 +72,5 @@ task_return1			vvp_tests/task_return1.json
 task_return2			vvp_tests/task_return2.json
 task_return_fail1		vvp_tests/task_return_fail1.json
 task_return_fail2		vvp_tests/task_return_fail2.json
+timing_check_syntax		vvp_tests/timing_check_syntax.json
+timing_check_delayed_signals	vvp_tests/timing_check_delayed_signals.json
diff --git a/ivtest/vvp_tests/timing_check_delayed_signals.json b/ivtest/vvp_tests/timing_check_delayed_signals.json
new file mode 100644
index 000000000..b93e39f09
--- /dev/null
+++ b/ivtest/vvp_tests/timing_check_delayed_signals.json
@@ -0,0 +1,4 @@
+{
+    "type"          : "normal",
+    "source"        : "timing_check_delayed_signals.v"
+}