diff --git a/vvp/part.cc b/vvp/part.cc
index 5b11485ce..3b7f6e500 100644
--- a/vvp/part.cc
+++ b/vvp/part.cc
@@ -109,6 +109,21 @@ void vvp_fun_part_pv::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit)
       vvp_send_vec4_pv(port.ptr()->out, bit, base_, wid_, vwid_);
 }
 
+void vvp_fun_part_pv::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
+{
+      assert(port.port() == 0);
+
+      if (bit.size() != wid_) {
+	    cerr << "internal error: part_pv (strength-aware) data mismatch. "
+		 << "base_=" << base_ << ", wid_=" << wid_
+		 << ", vwid_=" << vwid_ << ", bit=" << bit
+		 << endl;
+      }
+      assert(bit.size() == wid_);
+
+      vvp_send_vec8_pv(port.ptr()->out, bit, base_, wid_, vwid_);
+}
+
 vvp_fun_part_var::vvp_fun_part_var(unsigned w)
 : base_(0), wid_(w)
 {
diff --git a/vvp/part.h b/vvp/part.h
index 8fa861b1a..3fdffd886 100644
--- a/vvp/part.h
+++ b/vvp/part.h
@@ -62,6 +62,7 @@ class vvp_fun_part_pv  : public vvp_net_fun_t {
 
     public:
       void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit);
+      void recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit);
 
     private:
       unsigned base_;
diff --git a/vvp/resolv.cc b/vvp/resolv.cc
index 4448b15c8..d0db6ec3c 100644
--- a/vvp/resolv.cc
+++ b/vvp/resolv.cc
@@ -97,6 +97,24 @@ void resolv_functor::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
       vvp_send_vec8(ptr->out, out);
 }
 
+void resolv_functor::recv_vec8_pv(vvp_net_ptr_t port, const vvp_vector8_t&bit,
+				  unsigned base, unsigned wid, unsigned vwid)
+{
+      assert(bit.size() == wid);
+      vvp_vector8_t res (vwid);
+
+      for (unsigned idx = 0 ;  idx < base ;  idx += 1)
+	    res.set_bit(idx, vvp_scalar_t());
+
+      for (unsigned idx = 0 ;  idx < wid ;  idx += 1)
+	    res.set_bit(idx+base, bit.value(idx));
+
+      for (unsigned idx = base+wid ;  idx < vwid ;  idx += 1)
+	    res.set_bit(idx, vvp_scalar_t());
+
+      recv_vec8(port, res);
+}
+
 resolv_wired_logic::resolv_wired_logic()
 {
 }
diff --git a/vvp/resolv.h b/vvp/resolv.h
index d7aa6fe94..4f0e683c6 100644
--- a/vvp/resolv.h
+++ b/vvp/resolv.h
@@ -45,6 +45,8 @@ class resolv_functor : public vvp_net_fun_t {
 
       void recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
 			unsigned base, unsigned wid, unsigned vwid);
+      void recv_vec8_pv(vvp_net_ptr_t port, const vvp_vector8_t&bit,
+			unsigned base, unsigned wid, unsigned vwid);
 
     private:
       vvp_vector8_t val_[4];
diff --git a/vvp/vvp_net.cc b/vvp/vvp_net.cc
index eb5f154b4..f038777a2 100644
--- a/vvp/vvp_net.cc
+++ b/vvp/vvp_net.cc
@@ -2123,7 +2123,16 @@ void vvp_net_fun_t::recv_vec4_pv(vvp_net_ptr_t, const vvp_vector4_t&bits,
 				 unsigned base, unsigned wid, unsigned vwid)
 {
       cerr << "internal error: " << typeid(*this).name() << ": "
-	   << "recv_vect_pv(" << bits << ", " << base
+	   << "recv_vec4_pv(" << bits << ", " << base
+	   << ", " << wid << ", " << vwid << ") not implemented" << endl;
+      assert(0);
+}
+
+void vvp_net_fun_t::recv_vec8_pv(vvp_net_ptr_t, const vvp_vector8_t&bits,
+				 unsigned base, unsigned wid, unsigned vwid)
+{
+      cerr << "internal error: " << typeid(*this).name() << ": "
+	   << "recv_vec8_pv(" << bits << ", " << base
 	   << ", " << wid << ", " << vwid << ") not implemented" << endl;
       assert(0);
 }
@@ -2402,6 +2411,12 @@ void vvp_fun_signal::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
       }
 }
 
+void vvp_fun_signal::recv_vec8_pv(vvp_net_ptr_t ptr, const vvp_vector8_t&bit,
+				  unsigned base, unsigned wid, unsigned vwid)
+{
+      recv_vec4_pv(ptr, reduce4(bit), base, wid, vwid);
+}
+
 void vvp_fun_signal::calculate_output_(vvp_net_ptr_t ptr)
 {
       if (force_mask_.size()) {
diff --git a/vvp/vvp_net.h b/vvp/vvp_net.h
index 2d352c4e3..6e6497179 100644
--- a/vvp/vvp_net.h
+++ b/vvp/vvp_net.h
@@ -870,6 +870,8 @@ class vvp_net_fun_t {
 	// Part select variants of above
       virtual void recv_vec4_pv(vvp_net_ptr_t p, const vvp_vector4_t&bit,
 				unsigned base, unsigned wid, unsigned vwid);
+      virtual void recv_vec8_pv(vvp_net_ptr_t p, const vvp_vector8_t&bit,
+				unsigned base, unsigned wid, unsigned vwid);
       virtual void recv_long_pv(vvp_net_ptr_t port, long bit,
                                 unsigned base, unsigned wid);
 
@@ -1114,6 +1116,8 @@ class vvp_fun_signal  : public vvp_fun_signal_vec {
 	// Part select variants of above
       void recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
 			unsigned base, unsigned wid, unsigned vwid);
+      void recv_vec8_pv(vvp_net_ptr_t port, const vvp_vector8_t&bit,
+			unsigned base, unsigned wid, unsigned vwid);
 
 	// Get information about the vector value.
       unsigned   size() const;
@@ -1320,4 +1324,17 @@ inline void vvp_send_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&val,
       }
 }
 
+inline void vvp_send_vec8_pv(vvp_net_ptr_t ptr, const vvp_vector8_t&val,
+		      unsigned base, unsigned wid, unsigned vwid)
+{
+      while (struct vvp_net_t*cur = ptr.ptr()) {
+	    vvp_net_ptr_t next = cur->port[ptr.port()];
+
+	    if (cur->fun)
+		  cur->fun->recv_vec8_pv(ptr, val, base, wid, vwid);
+
+	    ptr = next;
+      }
+}
+
 #endif