diff --git a/Documentation/usage/icarus_verilog_extensions.rst b/Documentation/usage/icarus_verilog_extensions.rst
index 7352a70c5..282840ccc 100644
--- a/Documentation/usage/icarus_verilog_extensions.rst
+++ b/Documentation/usage/icarus_verilog_extensions.rst
@@ -2,25 +2,29 @@
 Icarus Verilog Extensions
 =========================
 
-Icarus Verilog supports certain extensions to the baseline IEEE1364
+Icarus Verilog supports certain extensions to the baseline IEEE 1364
 standard. Some of these are picked from extended variants of the
 language, such as SystemVerilog, and some are expressions of internal
 behavior of Icarus Verilog, made available as a tool debugging aid.
 
-* Builtin System Functions
+Built-in System Functions
+-------------------------
 
-** Extended Verilog Data Types
+Extended Verilog Data Types
+---------------------------
 
-This feature is turned off if the generation flag "-g" is set to other
-then the default "2x".  For example, "iverilog -g2x" enables extended
-data types, and "iverilog -g2" disables them.
+This feature is turned on by the generation flag "-gxtypes" and turned
+off by the generation flag "-gno-xtypes". It is turned on by default.
 
 Icarus Verilog adds support for extended data types. This extended
 type syntax is based on a proposal by Cadence Design Systems,
-originally as an update to the IEEE1364. That original proposal has
-apparently been absorbed by the IEEE1800 SystemVerilog
-standard. Icarus Verilog currently only takes the new primitive types
-from the proposal.
+originally as an update to the IEEE 1364 standard. Icarus Verilog
+currently only takes the new primitive types from the proposal.
+
+SystemVerilog provides the same functionality using somewhat different
+syntax. This extension is maintained for backwards compatibility.
+
+- Types
 
 Extended data types separates the concept of net/variable from the
 data type. Both nets and variables can declared with any data
@@ -28,7 +32,7 @@ type. The primitive types available are::
 
     logic  - The familiar 0, 1, x and z, optionally with strength.
     bool   - Limited to only 0 and 1
-    real   - 64bit real values
+    real   - 64-bit real values
 
 Nets with logic type may have multiple drivers with strength, and the
 value is resolved the usual way. Only logic values may be driven to
@@ -61,9 +65,9 @@ types as nets.
 - Ports
 
 Module and task ports in standard Verilog are restricted to logic
-types. This extension removes that restriction, allowing any type to
-pass through the port consistent with the continuous assignment
-connectivity that is implied by the type.
+types. This extension removes that restriction, allowing any of
+the above types to pass through the port consistent with the
+continuous assignment connectivity that is implied by the type.
 
 - Expressions
 
@@ -81,5 +85,6 @@ bools and reals always return exactly true or false.
 Case comparison returns bool. This differs from baseline Verilog,
 which strictly speaking returns a logic, but only 0 or 1 values.
 
-All the arithmetic operators return bool if both of their operands are
-bool or real. Otherwise, they return logic.
+Arithmetic operators return real if either of their operands is real,
+otherwise they return logic if either of their operands is logic. If
+both operands are bool, they return bool.