diff --git a/elab_sig.cc b/elab_sig.cc
index 734d0dfdd..5dabe9c26 100644
--- a/elab_sig.cc
+++ b/elab_sig.cc
@@ -1210,7 +1210,8 @@ NetNet* PWire::elaborate_sig(Design*des, NetScope*scope)
 
       NetNet*sig = new NetNet(scope, name_, wtype, unpacked_dimensions, type);
 
-      if (wtype == NetNet::WIRE) sig->devirtualize_pins();
+      if (wtype == NetNet::WIRE || wtype == NetNet::UNRESOLVED_WIRE)
+	    sig->devirtualize_pins();
       sig->set_line(*this);
       sig->port_type(port_type_);
       sig->lexical_pos(lexical_pos_);
diff --git a/ivtest/ivltests/br_gh1220.v b/ivtest/ivltests/br_gh1220.v
new file mode 100644
index 000000000..c8218b7e8
--- /dev/null
+++ b/ivtest/ivltests/br_gh1220.v
@@ -0,0 +1,19 @@
+// Test for GitHub issue #1220
+// Assertion failed with uwire multi-dimensional input port
+module sub(input uwire data [1:0]);
+  initial begin
+    #1;
+    if (data[0] === 1'b0 && data[1] === 1'b1)
+      $display("PASSED");
+    else
+      $display("FAILED: data[0]=%0b data[1]=%0b", data[0], data[1]);
+  end
+endmodule
+
+module test;
+  wire w [1:0];
+  assign w[0] = 1'b0;
+  assign w[1] = 1'b1;
+
+  sub dut(.data(w));
+endmodule
diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list
index 830218e2d..82b28c304 100644
--- a/ivtest/regress-sv.list
+++ b/ivtest/regress-sv.list
@@ -229,6 +229,7 @@ br_gh782b		normal,-g2009		ivltests gold=br_gh782b.gold
 br_gh800		normal,-g2009		ivltests
 br_gh801		normal,-g2012		ivltests
 br_gh801b		normal,-g2012		ivltests
+br_gh1220		normal,-g2012		ivltests
 br_gh1222		CE,-g2009		ivltests gold=br_gh1222.gold
 br_gh1223a		normal,-g2009		ivltests
 br_gh1223b		normal,-g2009		ivltests
diff --git a/t-dll-api.cc b/t-dll-api.cc
index 7a33018f8..a3a5fcf28 100644
--- a/t-dll-api.cc
+++ b/t-dll-api.cc
@@ -2496,8 +2496,8 @@ extern "C" ivl_nexus_t ivl_signal_nex(ivl_signal_t net, unsigned word)
 	    if (net->pins) {
 		return net->pins[word];
 	    } else {
-		// net->pins can be NULL for a virtualized reg array.
-		assert(net->type_ == IVL_SIT_REG);
+		// net->pins can be NULL for a virtualized reg or uwire array.
+		assert(net->type_ == IVL_SIT_REG || net->type_ == IVL_SIT_UWIRE);
 		return NULL;
 	    }
       } else {