From 7250337941e9811cfcee32134ab83ae234d46454 Mon Sep 17 00:00:00 2001 From: steve Date: Fri, 28 Jan 2005 19:39:03 +0000 Subject: [PATCH] Integrate fixes from 0.8 branch. --- tgt-vvp/vvp_process.c | 56 ++++++++++++++++++++++++++++--------------- 1 file changed, 37 insertions(+), 19 deletions(-) diff --git a/tgt-vvp/vvp_process.c b/tgt-vvp/vvp_process.c index fb51af5dd..85887627f 100644 --- a/tgt-vvp/vvp_process.c +++ b/tgt-vvp/vvp_process.c @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: vvp_process.c,v 1.97 2004/12/18 18:53:26 steve Exp $" +#ident "$Id: vvp_process.c,v 1.98 2005/01/28 19:39:03 steve Exp $" #endif # include "vvp_priv.h" @@ -163,18 +163,39 @@ static void assign_to_memory(ivl_memory_t mem, unsigned idx, * This function, in addition to setting the value into index 0, sets * bit 4 to 1 if the value is unknown. */ +void draw_eval_expr_into_integer(ivl_expr_t expr, unsigned ix) +{ + struct vector_info vec; + int word; + + switch (ivl_expr_value(expr)) { + + case IVL_VT_VECTOR: + vec = draw_eval_expr(expr, 0); + fprintf(vvp_out, " %%ix/get %u, %u, %u;\n", + ix, vec.base, vec.wid); + clr_vector(vec); + break; + + case IVL_VT_REAL: + word = draw_eval_real(expr); + clr_word(word); + fprintf(vvp_out, " %%cvt/ir %u, %u;\n", ix, word); + break; + + default: + assert(0); + } +} + static void calculate_into_x0(ivl_expr_t expr) { - struct vector_info vec = draw_eval_expr(expr, 0); - fprintf(vvp_out, " %%ix/get 0, %u, %u;\n", vec.base, vec.wid); - clr_vector(vec); + draw_eval_expr_into_integer(expr, 0); } static void calculate_into_x1(ivl_expr_t expr) { - struct vector_info vec = draw_eval_expr(expr, 0); - fprintf(vvp_out, " %%ix/get 1, %u, %u;\n", vec.base, vec.wid); - clr_vector(vec); + draw_eval_expr_into_integer(expr, 1); } /* @@ -445,7 +466,7 @@ static int show_stmt_assign(ivl_statement_t net) * This function handles the case of non-blocking assign to word * variables such as real, i.e: * - * read foo; + * real foo; * foo <= 1.0; * * In this case we know (by Verilog syntax) that there is only exactly @@ -483,6 +504,8 @@ static int show_stmt_assign_nb_var(ivl_statement_t net) fprintf(vvp_out, " %%assign/wr W_%s, %lu, %u;\n", vvp_word_label(var), delay, word); + clr_word(word); + return 0; } @@ -1537,19 +1560,14 @@ int draw_func_definition(ivl_scope_t scope) /* * $Log: vvp_process.c,v $ - * Revision 1.97 2004/12/18 18:53:26 steve - * Use %set/v to trigger events. + * Revision 1.98 2005/01/28 19:39:03 steve + * Integrate fixes from 0.8 branch. * - * Revision 1.96 2004/12/17 04:46:40 steve - * Implement release functionality. + * Revision 1.93.2.2 2005/01/28 18:29:29 steve + * Add ability to compile real values into index registers. * - * Revision 1.95 2004/12/11 05:43:30 steve - * cassign and deassign handle concatenated l-values. - * - * Revision 1.94 2004/12/11 02:31:28 steve - * Rework of internals to carry vectors through nexus instead - * of single bits. Make the ivl, tgt-vvp and vvp initial changes - * down this path. + * Revision 1.93.2.1 2004/12/12 04:25:10 steve + * Fix leak of word registers in code generator. * * Revision 1.93 2004/10/04 01:10:57 steve * Clean up spurious trailing white space.