From 6f5f700cb9fa256f747fe7b1d1f63be078f70f8a Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Thu, 7 Aug 2008 10:54:39 +0100 Subject: [PATCH] Very minimal implementation of tasks This expands the task in-line inside the process to avoid problems with global variables (VHDL processes cannot reference globals) --- tgt-vhdl/stmt.cc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc index fff4760a4..43e3a3f7e 100644 --- a/tgt-vhdl/stmt.cc +++ b/tgt-vhdl/stmt.cc @@ -609,6 +609,24 @@ int draw_repeat(vhdl_procedural *proc, stmt_container *container, return 0; } +/* + * Tasks are difficult to translate to VHDL since they allow things + * not allowed by VHDL's corresponding procedures (e.g. updating + * global variables. The solution here is to expand tasks in-line. + */ +int draw_utask(vhdl_procedural *proc, stmt_container *container, + ivl_statement_t stmt) +{ + ivl_scope_t tscope = ivl_stmt_call(stmt); + + // TODO: adding some comments to the output would be helpful + + // TOOD: this completely ignores paremeters! + draw_stmt(proc, container, ivl_scope_def(tscope), false); + + return 0; +} + /* * Generate VHDL statements for the given Verilog statement and * add them to the given VHDL process. The container is the @@ -651,6 +669,8 @@ int draw_stmt(vhdl_procedural *proc, stmt_container *container, return draw_forever(proc, container, stmt); case IVL_ST_REPEAT: return draw_repeat(proc, container, stmt); + case IVL_ST_UTASK: + return draw_utask(proc, container, stmt); default: error("No VHDL translation for statement at %s:%d (type = %d)", ivl_stmt_file(stmt), ivl_stmt_lineno(stmt),