diff --git a/tgt-vhdl/expr.cc b/tgt-vhdl/expr.cc
index 78cb14b37..3501bc188 100644
--- a/tgt-vhdl/expr.cc
+++ b/tgt-vhdl/expr.cc
@@ -23,11 +23,29 @@
 #include <iostream>
 #include <cassert>
 
+/*
+ * Convert a constant Verilog string to a constant VHDL string.
+ */
+static vhdl_expr *translate_string(ivl_expr_t e)
+{   
+   // TODO: May need to inspect or escape parts of this
+   const char *str = ivl_expr_string(e);
+   return new vhdl_const_string(str);
+}
 
 /*
  * Generate a VHDL expression from a Verilog expression.
  */
 vhdl_expr *translate_expr(ivl_expr_t e)
 {
-   assert(false);
+   ivl_expr_type_t type = ivl_expr_type(e);
+
+   switch (type) {
+   case IVL_EX_STRING:
+      return translate_string(e);
+   default:
+      error("No VHDL translation for expression at %s:%d (type = %d)",
+            ivl_expr_file(e), ivl_expr_lineno(e), type);
+      return NULL;
+   }
 }
diff --git a/tgt-vhdl/process.cc b/tgt-vhdl/process.cc
index 3a6cf7744..f0945b86a 100644
--- a/tgt-vhdl/process.cc
+++ b/tgt-vhdl/process.cc
@@ -31,7 +31,6 @@
  */
 static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
 {
-   
    // Create a new process and store it in the entity's
    // architecture. This needs to be done first or the
    // parent link won't be valid (and draw_stmt needs this
diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc
index 9d97a75c9..d64ff8253 100644
--- a/tgt-vhdl/stmt.cc
+++ b/tgt-vhdl/stmt.cc
@@ -52,14 +52,30 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
       proc->add_decl(line_var);
    }
 
-   // TODO: Write the data into the line
+   
+
+   // Write the data into the line
+   int count = ivl_stmt_parm_count(stmt);
+   for (int i = 0; i < count; i++) {
+      // TODO: This is a bit simplistic since it will only
+      // work with strings
+      // --> Need to add a call to Type'Image for non-string
+      //     expressions
+      vhdl_expr *e = translate_expr(ivl_stmt_parm(stmt, i));
+      if (NULL == e)
+         return 1;
+
+      vhdl_pcall_stmt *write = new vhdl_pcall_stmt("Write");
+      write->add_expr(new vhdl_var_ref(display_line));
+      write->add_expr(e);
+
+      proc->add_stmt(write);
+   }
 
    // WriteLine(Output, Verilog_Display_Line)
-   vhdl_var_ref *output_ref = new vhdl_var_ref("Output");
-   vhdl_var_ref *line_ref = new vhdl_var_ref(display_line);
    vhdl_pcall_stmt *write_line = new vhdl_pcall_stmt("WriteLine");
-   write_line->add_expr(output_ref);
-   write_line->add_expr(line_ref);
+   write_line->add_expr(new vhdl_var_ref("Output"));
+   write_line->add_expr(new vhdl_var_ref(display_line));
    proc->add_stmt(write_line);
    
    return 0;
diff --git a/tgt-vhdl/vhdl_element.cc b/tgt-vhdl/vhdl_element.cc
index c2e4a6b7d..c2e77aacd 100644
--- a/tgt-vhdl/vhdl_element.cc
+++ b/tgt-vhdl/vhdl_element.cc
@@ -354,3 +354,8 @@ void vhdl_var_ref::emit(std::ofstream &of, int level) const
 {
    of << name_;
 }
+
+void vhdl_const_string::emit(std::ofstream &of, int level) const
+{
+   of << "\"" << value_ << "\"";
+}
diff --git a/tgt-vhdl/vhdl_element.hh b/tgt-vhdl/vhdl_element.hh
index 553dcb013..38fe6b537 100644
--- a/tgt-vhdl/vhdl_element.hh
+++ b/tgt-vhdl/vhdl_element.hh
@@ -83,6 +83,15 @@ private:
    std::string name_;
 };
 
+class vhdl_const_string : public vhdl_expr {
+public:
+   vhdl_const_string(const char *value) : value_(value) {}
+
+   void emit(std::ofstream &of, int level) const;
+private:
+   std::string value_;
+};
+
 class vhdl_expr_list : public vhdl_element {
 public:
    ~vhdl_expr_list();