From 6da47b1eba3d7b2ce485c71f1ed085d1f6df750d Mon Sep 17 00:00:00 2001 From: Cary R Date: Wed, 24 Mar 2010 19:28:28 -0700 Subject: [PATCH] Perform bit <-> real conversions for module inputs. This patch makes the compiler perform either bit to real or real to bit conversion when needed on module input signals. (cherry picked from commit 8e697648343ebb5362a2b58076aa040edf9457f2) --- elaborate.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/elaborate.cc b/elaborate.cc index 3f8f6a0d1..0cacecc7c 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -1286,6 +1286,22 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const sig = tmp2; } + // If we have a real signal driving a bit/vector port + // then we convert the real value using the appropriate + // width cast. Since a real is only one bit the whole + // thing needs to go to each instance when arrayed. + if ((sig->data_type() == IVL_VT_REAL ) && + prts.size() && (prts[0]->data_type() != IVL_VT_REAL )) { + sig = cast_to_int(des, scope, sig, + prts_vector_width/instance.size()); + } + // If we have a bit/vector signal driving a real port + // then we convert the value to a real. + if ((sig->data_type() != IVL_VT_REAL ) && + prts.size() && (prts[0]->data_type() == IVL_VT_REAL )) { + sig = cast_to_real(des, scope, sig); + } + } else if (prts[0]->port_type() == NetNet::PINOUT) { /* Inout to/from module. This is a more