From 6b73cc39a54526a471b97c4b0fcc62a679fdaf5c Mon Sep 17 00:00:00 2001
From: Nick Gasson <nick@nickg.me.uk>
Date: Mon, 7 Jul 2008 16:17:54 +0100
Subject: [PATCH] Add Active_High support func and fix LPM part select

---
 tgt-vhdl/lpm.cc              |  4 ++--
 tgt-vhdl/verilog_support.vhd | 15 +++++++++++++--
 tgt-vhdl/vhdl_syntax.cc      | 10 ++++++++++
 3 files changed, 25 insertions(+), 4 deletions(-)

diff --git a/tgt-vhdl/lpm.cc b/tgt-vhdl/lpm.cc
index 12288e725..d0e20217d 100644
--- a/tgt-vhdl/lpm.cc
+++ b/tgt-vhdl/lpm.cc
@@ -89,7 +89,7 @@ static int draw_part_select_vp_lpm(vhdl_arch *arch, ivl_lpm_t lpm)
    if (NULL == out)
       return 1;
 
-   selfrom->set_slice(off);
+   selfrom->set_slice(off, ivl_lpm_width(lpm) - 1);
    arch->add_stmt(new vhdl_cassign_stmt(out, selfrom));
    return 0;
 }
@@ -108,7 +108,7 @@ static int draw_part_select_pv_lpm(vhdl_arch *arch, ivl_lpm_t lpm)
    if (NULL == out)
       return 1;
 
-   out->set_slice(off);
+   out->set_slice(off, ivl_lpm_width(lpm) - 1);
    arch->add_stmt(new vhdl_cassign_stmt(out, selfrom));
    return 0;
 }
diff --git a/tgt-vhdl/verilog_support.vhd b/tgt-vhdl/verilog_support.vhd
index b1c4f7e32..34ec5df20 100644
--- a/tgt-vhdl/verilog_support.vhd
+++ b/tgt-vhdl/verilog_support.vhd
@@ -15,7 +15,9 @@ package Verilog_Support is
 
   -- Routines to implement Verilog reduction operators
   function Reduce_OR(X : unsigned) return std_logic;
-  
+
+  -- Convert Boolean to std_logic
+  function Active_High(B : Boolean) return std_logic;
   
 end Verilog_Support;
 
@@ -36,6 +38,15 @@ package body Verilog_Support is
       end if;
     end loop;
     return '0';
-  end function;  
+  end function;
+
+  function Active_High(B : Boolean) return std_logic is
+  begin
+    if B then
+      return '1';
+    else
+      return '0';
+    end if;
+  end function;      
   
 end Verilog_Support;
diff --git a/tgt-vhdl/vhdl_syntax.cc b/tgt-vhdl/vhdl_syntax.cc
index aa5d18eb7..df07bff65 100644
--- a/tgt-vhdl/vhdl_syntax.cc
+++ b/tgt-vhdl/vhdl_syntax.cc
@@ -400,6 +400,16 @@ vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
 
       return conv;
    }
+   else if (to->get_name() == VHDL_TYPE_STD_LOGIC &&
+            type_->get_name() == VHDL_TYPE_BOOLEAN) {
+      // Verilog assumes active-high logic and there
+      // is a special routine in verilog_support.vhd
+      // to do this for us
+      vhdl_fcall *ah = new vhdl_fcall("Active_High", vhdl_type::std_logic());
+      ah->add_expr(this);
+
+      return ah;
+   }
    else {
       // We have to cast the expression before resizing or the
       // wrong sign bit may be extended (i.e. when casting between