From 63a8b4abe2ce9777bef6fda0939a64af051ab90d Mon Sep 17 00:00:00 2001 From: steve Date: Sun, 20 Dec 1998 02:05:41 +0000 Subject: [PATCH] Function to calculate wire initial value. --- Makefile | 2 +- design_dump.cc | 10 ++++-- main.cc | 7 +++- netlist.h | 24 ++++++++++++-- propinit.cc | 88 +++++++++++++++++++++++++++++++++++++++++++++++++ t-vvm.cc | 36 +++++++++++++++++--- verinum.cc | 14 +++++++- verinum.h | 6 +++- vvm/vvm_gates.h | 21 ++++++++++-- 9 files changed, 193 insertions(+), 15 deletions(-) create mode 100644 propinit.cc diff --git a/Makefile b/Makefile index 2467d2d20..8c796e7a6 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ CXXFLAGS = -O -g -Wall -Wno-uninitialized #TT = t-debug.o t-vvm.o TT = t-verilog.o t-vvm.o t-xnf.o -FF = nobufz.o sigfold.o stupid.o xnfio.o +FF = nobufz.o propinit.o sigfold.o stupid.o xnfio.o O = main.o cprop.o design_dump.o elaborate.o emit.o eval.o lexor.o mangle.o \ netlist.o parse.o parse_misc.o pform.o pform_dump.o verinum.o target.o \ diff --git a/design_dump.cc b/design_dump.cc index a37abbeae..0a02a6bd1 100644 --- a/design_dump.cc +++ b/design_dump.cc @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: design_dump.cc,v 1.8 1998/12/14 02:01:34 steve Exp $" +#ident "$Id: design_dump.cc,v 1.9 1998/12/20 02:05:41 steve Exp $" #endif /* @@ -50,7 +50,10 @@ void NetNet::dump_net(ostream&o, unsigned ind) const if (local_flag_) o << " (local)"; o << " #(" << delay1() << "," << delay2() << "," << delay3() << - ")" << endl; + ") init="; + for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1) + o << ivalue_[idx-1]; + o << endl; dump_obj_attr(o, ind+4); } @@ -461,6 +464,9 @@ void Design::dump(ostream&o) const /* * $Log: design_dump.cc,v $ + * Revision 1.9 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.8 1998/12/14 02:01:34 steve * Fully elaborate Sequential UDP behavior. * diff --git a/main.cc b/main.cc index 19f994767..15f4a342f 100644 --- a/main.cc +++ b/main.cc @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: main.cc,v 1.10 1998/12/09 04:02:47 steve Exp $" +#ident "$Id: main.cc,v 1.11 1998/12/20 02:05:41 steve Exp $" #endif # include @@ -60,6 +60,7 @@ extern Design* elaborate(const map&modules, extern void emit(ostream&o, const Design*, const char*); extern void cprop(Design*des); +extern void propinit(Design*des); extern void sigfold(Design*des); extern void stupid(Design*des); extern void nobufz(Design*des); @@ -72,6 +73,7 @@ static struct net_func_map { } func_table[] = { { "cprop", &cprop }, { "nobufz", &nobufz }, + { "propinit", &propinit }, { "sigfold", &sigfold }, { "stupid", &stupid }, { "xnfio", &xnfio }, @@ -222,6 +224,9 @@ int main(int argc, char*argv[]) /* * $Log: main.cc,v $ + * Revision 1.11 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.10 1998/12/09 04:02:47 steve * Support the include directive. * diff --git a/netlist.h b/netlist.h index 462b38fc7..e208ddc1f 100644 --- a/netlist.h +++ b/netlist.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: netlist.h,v 1.14 1998/12/18 05:16:25 steve Exp $" +#ident "$Id: netlist.h,v 1.15 1998/12/20 02:05:41 steve Exp $" #endif /* @@ -220,12 +220,20 @@ class NetNet : public NetObj { explicit NetNet(const string&n, Type t, unsigned npins =1) : NetObj(n, npins), sig_next_(0), sig_prev_(0), design_(0), type_(t), port_type_(NOT_A_PORT), msb_(npins-1), lsb_(0), - local_flag_(false) { } + local_flag_(false) + { ivalue_ = new verinum::V[npins]; + for (unsigned idx = 0 ; idx < npins ; idx += 1) + ivalue_[idx] = verinum::Vz; + } explicit NetNet(const string&n, Type t, long ms, long ls) : NetObj(n, ((ms>ls)?ms-ls:ls-ms) + 1), sig_next_(0), sig_prev_(0), design_(0), type_(t), port_type_(NOT_A_PORT), - msb_(ms), lsb_(ls), local_flag_(false) { } + msb_(ms), lsb_(ls), local_flag_(false) + { ivalue_ = new verinum::V[pin_count()]; + for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) + ivalue_[idx] = verinum::Vz; + } virtual ~NetNet(); @@ -249,6 +257,11 @@ class NetNet : public NetObj { bool local_flag() const { return local_flag_; } void local_flag(bool f) { local_flag_ = f; } + verinum::V get_ival(unsigned pin) const + { return ivalue_[pin]; } + void set_ival(unsigned pin, verinum::V val) + { ivalue_[pin] = val; } + virtual void dump_net(ostream&, unsigned) const; private: @@ -264,6 +277,8 @@ class NetNet : public NetObj { long msb_, lsb_; bool local_flag_; + + verinum::V*ivalue_; }; /* @@ -906,6 +921,9 @@ extern ostream& operator << (ostream&, NetNet::Type); /* * $Log: netlist.h,v $ + * Revision 1.15 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.14 1998/12/18 05:16:25 steve * Parse more UDP input edge descriptions. * diff --git a/propinit.cc b/propinit.cc new file mode 100644 index 000000000..3c80a9e10 --- /dev/null +++ b/propinit.cc @@ -0,0 +1,88 @@ +/* + * Copyright (c) 1998 Stephen Williams (steve@picturel.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ +#if !defined(WINNT) +#ident "$Id: propinit.cc,v 1.1 1998/12/20 02:05:41 steve Exp $" +#endif + +/* + * The propinit function runs through the devices that can impose + * initial values in the netlist and propogates those values. The + * process works by first scanning the active devices for outputs that + * they generate. + */ + +# include "netlist.h" + +/* + * prop_sequdp_output takes the output from the located sequential UDP + * device and propogates it to the signals connected to it. + */ +static bool is_sequ_udp(const NetNode*net) +{ + const NetUDP*udp; + if ((udp = dynamic_cast(net)) == 0) + return false; + + return udp->is_sequential(); +} + +static void prop_sequdp_output(NetUDP*udp) +{ + /* Get from the UDP class the initial output value. */ + verinum::V ival; + switch (udp->get_initial()) { + case '0': + ival = verinum::V0; + break; + case '1': + ival = verinum::V1; + break; + default: + ival = verinum::Vx; + break; + } + + /* Take the output value and write it to all the NetNet pins + that are connected to the output pin. */ + + for (NetObj::Link*lnk = udp->pin(0).next_link() + ; (*lnk) != udp->pin(0) ; lnk = lnk->next_link()) { + + if (NetNet*sig = dynamic_cast(lnk->get_obj())) + sig->set_ival(lnk->get_pin(), ival); + + } +} + +void propinit(Design*des) +{ + des->clear_node_marks(); + while (NetNode*net = des->find_node(&is_sequ_udp)) { + net->set_mark(); + prop_sequdp_output(dynamic_cast(net)); + } +} + +/* + * $Log: propinit.cc,v $ + * Revision 1.1 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * + */ + diff --git a/t-vvm.cc b/t-vvm.cc index 5fdd79d6b..d88c2e013 100644 --- a/t-vvm.cc +++ b/t-vvm.cc @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: t-vvm.cc,v 1.7 1998/12/17 23:54:58 steve Exp $" +#ident "$Id: t-vvm.cc,v 1.8 1998/12/20 02:05:41 steve Exp $" #endif # include @@ -261,6 +261,9 @@ void target_vvm::start_design(ostream&os, const Design*mod) os << "# include \"vvm_calltf.h\"" << endl; os << "# include \"vvm_thread.h\"" << endl; process_counter = 0; + + init_code << "static void design_init(vvm_simulation&sim)" << endl; + init_code << "{" << endl; } void target_vvm::end_design(ostream&os, const Design*mod) @@ -268,11 +271,12 @@ void target_vvm::end_design(ostream&os, const Design*mod) delayed << ends; os << delayed.str(); + init_code << "}" << endl << ends; + os << init_code.str(); + os << "main()" << endl << "{" << endl; os << " vvm_simulation sim;" << endl; - - init_code << ends; - os << init_code.str(); + os << " design_init(sim);" << endl; for (unsigned idx = 0 ; idx < process_counter ; idx += 1) os << " thread" << (idx+1) << "_t thread_" << @@ -288,6 +292,24 @@ void target_vvm::signal(ostream&os, const NetNet*sig) mangle(sig->name()) << "; /* " << sig->name() << " */" << endl; os << "static vvm_monitor_t " << mangle(sig->name()) << "_mon(\"" << sig->name() << "\");" << endl; + + /* Scan the signals of the vector, passing the initial value + to the inputs of all the connected devices. */ + for (unsigned idx = 0 ; idx < sig->pin_count() ; idx += 1) { + if (sig->get_ival(idx) == verinum::Vz) + continue; + + for (NetObj::Link*lnk = sig->pin(0).next_link() + ; (*lnk) != sig->pin(0) ; lnk = lnk->next_link()) { + const NetNode*net; + if (net = dynamic_cast(lnk->get_obj())) { + init_code << " " << + mangle(lnk->get_obj()->name()) << + ".init(" << lnk->get_pin() << ", V" << + sig->get_ival(idx) << ");" << endl; + } + } + } } /* @@ -446,7 +468,10 @@ void target_vvm::udp(ostream&os, const NetUDP*gate) "_output_fun, V" << gate->get_initial() << ", " << mangle(gate->name()) << "_table);" << endl; + /* The UDP output function is much like other logic gates. Use + this general method to output the output function. */ emit_gate_outputfun_(gate); + } /* @@ -742,6 +767,9 @@ extern const struct target tgt_vvm = { }; /* * $Log: t-vvm.cc,v $ + * Revision 1.8 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.7 1998/12/17 23:54:58 steve * VVM support for small sequential UDP objects. * diff --git a/verinum.cc b/verinum.cc index 391e1b28f..bbdc7bb5d 100644 --- a/verinum.cc +++ b/verinum.cc @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: verinum.cc,v 1.5 1998/11/11 00:01:51 steve Exp $" +#ident "$Id: verinum.cc,v 1.6 1998/12/20 02:05:41 steve Exp $" #endif # include "verinum.h" @@ -60,6 +60,15 @@ verinum::verinum(const string&str) } } +verinum::verinum(verinum::V val, unsigned n) +: string_flag_(false) +{ + nbits_ = n; + bits_ = new V[nbits_]; + for (unsigned idx = 0 ; idx < nbits_ ; idx += 1) + bits_[idx] = val; +} + verinum::verinum(const verinum&that) { string_flag_ = that.string_flag_; @@ -221,6 +230,9 @@ bool operator == (const verinum&left, const verinum&right) /* * $Log: verinum.cc,v $ + * Revision 1.6 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.5 1998/11/11 00:01:51 steve * Check net ranges in declarations. * diff --git a/verinum.h b/verinum.h index a42162846..aaae5c2c6 100644 --- a/verinum.h +++ b/verinum.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: verinum.h,v 1.3 1998/11/11 00:01:51 steve Exp $" +#ident "$Id: verinum.h,v 1.4 1998/12/20 02:05:41 steve Exp $" #endif # include @@ -38,6 +38,7 @@ class verinum { verinum(); verinum(const string&str); verinum(const V*v, unsigned nbits); + verinum(V, unsigned nbits =1); verinum(unsigned long val, unsigned bits); verinum(const verinum&); ~verinum(); @@ -80,6 +81,9 @@ extern bool operator == (const verinum&left, const verinum&right); /* * $Log: verinum.h,v $ + * Revision 1.4 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.3 1998/11/11 00:01:51 steve * Check net ranges in declarations. * diff --git a/vvm/vvm_gates.h b/vvm/vvm_gates.h index 4a8162a62..a17c02060 100644 --- a/vvm/vvm_gates.h +++ b/vvm/vvm_gates.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if !defined(WINNT) -#ident "$Id: vvm_gates.h,v 1.3 1998/12/17 23:54:58 steve Exp $" +#ident "$Id: vvm_gates.h,v 1.4 1998/12/20 02:05:41 steve Exp $" #endif # include "vvm.h" @@ -55,6 +55,8 @@ template class vvm_and { explicit vvm_and(vvm_out_event::action_t o) : output_(o) { } + void init(unsigned idx, vvm_bit_t val) { input_[idx-1] = val; } + void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val) { if (input_[idx-1] == val) return; @@ -84,6 +86,8 @@ template class vvm_nand { input_[idx] = V0; } + void init(unsigned idx, vvm_bit_t val) { input_[idx-1] = val; } + // Set an input of the NAND gate causes a new output value to // be calculated and an event generated to make the output // happen. The input pins are numbered from 1 - WIDTH. @@ -109,7 +113,6 @@ template class vvm_nand { /* * Simple inverter buffer. - * XXXX The WIDTH parameter is useless? */ template class vvm_not { @@ -118,6 +121,8 @@ template class vvm_not { : output_(o) { } + void init(unsigned, vvm_bit_t) { } + void set(vvm_simulation*sim, unsigned, vvm_bit_t val) { vvm_bit_t outval = not(val); vvm_event*ev = new vvm_out_event(sim, outval, output_); @@ -137,6 +142,8 @@ template class vvm_xnor { explicit vvm_xnor(vvm_out_event::action_t o) : output_(o) { } + void init(unsigned idx, vvm_bit_t val) { input_[idx-1] = val; } + void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val) { if (input_[idx-1] == val) return; @@ -164,6 +171,8 @@ template class vvm_xor { explicit vvm_xor(vvm_out_event::action_t o) : output_(o) { } + void init(unsigned idx, vvm_bit_t val) { input_[idx-1] = val; } + void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val) { if (input_[idx-1] == val) return; @@ -202,6 +211,9 @@ template class vvm_udp_ssequ { state_[idx] = Vx; } + void init(unsigned pin, vvm_bit_t val) + { state_[pin] = val; } + void set(vvm_simulation*sim, unsigned pin, vvm_bit_t val) { assert(pin > 0); assert(pin < WIDTH+1); @@ -249,6 +261,8 @@ class vvm_bufz { : output_(o) { } + void init(unsigned idx, vvm_bit_t val) { } + void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val) { output_(sim, val); } @@ -278,6 +292,9 @@ class vvm_pevent { /* * $Log: vvm_gates.h,v $ + * Revision 1.4 1998/12/20 02:05:41 steve + * Function to calculate wire initial value. + * * Revision 1.3 1998/12/17 23:54:58 steve * VVM support for small sequential UDP objects. *