diff --git a/ivtest/vpi/sim_time_cb.c b/ivtest/vpi/sim_time_cb.c
index acb829972..953905973 100644
--- a/ivtest/vpi/sim_time_cb.c
+++ b/ivtest/vpi/sim_time_cb.c
@@ -6,6 +6,7 @@
 
 #include <vpi_user.h>
 #include <stdlib.h>
+#include <string.h>
 #include <assert.h>
 
 static PLI_INT32 monitor_cb(p_cb_data cb_data)
@@ -16,12 +17,14 @@ static PLI_INT32 monitor_cb(p_cb_data cb_data)
     s_vpi_value value;
     PLI_INT32   index;
 
-    time.type = TIME_TYPE;
-    vpi_get_time(var_list[0], &time);
-#ifdef TEST_SCALED_TIME
-    vpi_printf(" @ %1.1f :", time.real);
-#else
+    time.type = vpiSimTime;
+    vpi_get_time(NULL, &time);
     vpi_printf(" @ %04d :", time.low);
+
+#ifdef TEST_SCALED_TIME
+    vpi_printf(" cb_data.time = %1.1f :", cb_data->time->real);
+#else
+    vpi_printf(" cb_data.time = %04d :", cb_data->time->low);
 #endif
 
     value.format = vpiIntVal;
@@ -124,15 +127,19 @@ static PLI_INT32 monitor_calltf(char*xx)
     time.low += delay.low;
 #endif
 
+    memset(&cb_data, 0, sizeof(cb_data));
+
     cb_data.reason    = cbAtStartOfSimTime;
     cb_data.cb_rtn    = monitor_cb_start;
     cb_data.user_data = (char*)var_list;
+    cb_data.obj       = var_list[0];
     cb_data.time      = &time;
     vpi_register_cb(&cb_data);
 
     cb_data.reason    = cbAfterDelay;
     cb_data.cb_rtn    = monitor_cb_delay;
     cb_data.user_data = (char*)var_list;
+    cb_data.obj       = var_list[0];
     cb_data.time      = &delay;
     vpi_register_cb(&cb_data);
 
@@ -141,15 +148,20 @@ static PLI_INT32 monitor_calltf(char*xx)
     cb_data.reason    = cbReadWriteSynch;
     cb_data.cb_rtn    = monitor_cb_synch;
     cb_data.user_data = (char*)var_list;
+    cb_data.obj       = var_list[0];
     cb_data.time      = &delay;
     vpi_register_cb(&cb_data);
 
     cb_data.reason    = cbAtEndOfSimTime;
     cb_data.cb_rtn    = monitor_cb_end;
     cb_data.user_data = (char*)var_list;
+    cb_data.obj       = var_list[0];
     cb_data.time      = &time;
     vpi_register_cb(&cb_data);
 
+    memset(&cb_data, 0, sizeof(cb_data));
+    memset(&time   , 0, sizeof(time));
+
     return 0;
 }
 
diff --git a/ivtest/vpi/sim_time_cb2.v b/ivtest/vpi/sim_time_cb2.v
index cd547c2da..171759ad0 100644
--- a/ivtest/vpi/sim_time_cb2.v
+++ b/ivtest/vpi/sim_time_cb2.v
@@ -1,26 +1,34 @@
 `timescale 1s/1ms
 
-module test;
+module dut;
 
 reg [7:0] a, b;
 
+endmodule
+
+`timescale 1ms/1ms
+
+module test;
+
+dut dut();
+
 initial begin
-    a = 0; b = 0;
-    $monitor_time_slot(2.0, a, b);
-    $monitor_time_slot(5.0, a, b);
-    #1;
-    a = 1; b <= 1;
-    #1;
-    a = 2; b <= 2;
-    #1;
-    a = 3; b <= 3;
-    #1;
-    a = 4; b <= 4;
-    #1;
-    a = 5; b <= 5;
-    #1;
-    a = 6; b <= 6;
-    #1;
+    dut.a = 0; dut.b = 0;
+    $monitor_time_slot(2.0, dut.a, dut.b);
+    $monitor_time_slot(5.0, dut.a, dut.b);
+    #1000;
+    dut.a = 1; dut.b <= 1;
+    #1000;
+    dut.a = 2; dut.b <= 2;
+    #1000;
+    dut.a = 3; dut.b <= 3;
+    #1000;
+    dut.a = 4; dut.b <= 4;
+    #1000;
+    dut.a = 5; dut.b <= 5;
+    #1000;
+    dut.a = 6; dut.b <= 6;
+    #1000;
     $finish(0);
 end
 
diff --git a/ivtest/vpi_gold/sim_time_cb1.gold b/ivtest/vpi_gold/sim_time_cb1.gold
index d99e5379b..a479bac8b 100644
--- a/ivtest/vpi_gold/sim_time_cb1.gold
+++ b/ivtest/vpi_gold/sim_time_cb1.gold
@@ -1,10 +1,10 @@
 Compiling vpi/sim_time_cb1.c...
 Making sim_time_cb1.vpi from  sim_time_cb1.o...
-cbStartOfSimTime @ 2000 : a = 1 b = 1
-cbAfterDelay     @ 2000 : a = 1 b = 1
-cbReadWriteSynch @ 2000 : a = 2 b = 2
-cbEndOfSimTime   @ 2000 : a = 2 b = 2
-cbStartOfSimTime @ 5000 : a = 4 b = 4
-cbAfterDelay     @ 5000 : a = 4 b = 4
-cbReadWriteSynch @ 5000 : a = 5 b = 5
-cbEndOfSimTime   @ 5000 : a = 5 b = 5
+cbStartOfSimTime @ 2000 : cb_data.time = 2000 : a = 1 b = 1
+cbAfterDelay     @ 2000 : cb_data.time = 2000 : a = 1 b = 1
+cbReadWriteSynch @ 2000 : cb_data.time = 2000 : a = 2 b = 2
+cbEndOfSimTime   @ 2000 : cb_data.time = 2000 : a = 2 b = 2
+cbStartOfSimTime @ 5000 : cb_data.time = 5000 : a = 4 b = 4
+cbAfterDelay     @ 5000 : cb_data.time = 5000 : a = 4 b = 4
+cbReadWriteSynch @ 5000 : cb_data.time = 5000 : a = 5 b = 5
+cbEndOfSimTime   @ 5000 : cb_data.time = 5000 : a = 5 b = 5
diff --git a/ivtest/vpi_gold/sim_time_cb2.gold b/ivtest/vpi_gold/sim_time_cb2.gold
index 0ec0e5ae1..253377053 100644
--- a/ivtest/vpi_gold/sim_time_cb2.gold
+++ b/ivtest/vpi_gold/sim_time_cb2.gold
@@ -1,10 +1,10 @@
 Compiling vpi/sim_time_cb2.c...
 Making sim_time_cb2.vpi from  sim_time_cb2.o...
-cbStartOfSimTime @ 2.0 : a = 1 b = 1
-cbAfterDelay     @ 2.0 : a = 1 b = 1
-cbReadWriteSynch @ 2.0 : a = 2 b = 2
-cbEndOfSimTime   @ 2.0 : a = 2 b = 2
-cbStartOfSimTime @ 5.0 : a = 4 b = 4
-cbAfterDelay     @ 5.0 : a = 4 b = 4
-cbReadWriteSynch @ 5.0 : a = 5 b = 5
-cbEndOfSimTime   @ 5.0 : a = 5 b = 5
+cbStartOfSimTime @ 2000 : cb_data.time = 2.0 : a = 1 b = 1
+cbAfterDelay     @ 2000 : cb_data.time = 2.0 : a = 1 b = 1
+cbReadWriteSynch @ 2000 : cb_data.time = 2.0 : a = 2 b = 2
+cbEndOfSimTime   @ 2000 : cb_data.time = 2.0 : a = 2 b = 2
+cbStartOfSimTime @ 5000 : cb_data.time = 5.0 : a = 4 b = 4
+cbAfterDelay     @ 5000 : cb_data.time = 5.0 : a = 4 b = 4
+cbReadWriteSynch @ 5000 : cb_data.time = 5.0 : a = 5 b = 5
+cbEndOfSimTime   @ 5000 : cb_data.time = 5.0 : a = 5 b = 5