From 61381fd9cd43b4e2682bbfc86b72ae5abfea39f7 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 25 Jun 2023 19:36:19 -0700 Subject: [PATCH] Fix bit select on signed multi-dimensional packed array Bit selects on packed arrays are always unsigned and have a width of 1. Element selects on a multi-dimensional packed array are always unsigned and have the width of the element. At the moment a element or bit select on the last level element of a multi-dimensional signed array will incorrectly yield a signed expression. Commit 40b36337e2c8 ("Fix some bugs with packed array dimensions") added some special checks to fix the width on multi-dimensional array element selects. But this removed the unsigned attribute from bit selects. Commit 81947edaa5e9 ("A bit select is not the same as selecting part of a packed array") fixed this for single dimensional packed array, but left it broken for multi-dimensional arrays. Commit 7c024d6cab16 ("Fix width calculation for bit/part selects of multi-dimensioned packed arrays.") added some additional fixes for the width calculation, which make the special checks in the first commit unnecessary. We can now remove those checks which will give us the correct behavior in terms of the signedness of bit and element selects on both single- and multi-dimensional packed arrays. Signed-off-by: Lars-Peter Clausen --- elab_expr.cc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/elab_expr.cc b/elab_expr.cc index fa3d3f87d..1d7d99f1f 100644 --- a/elab_expr.cc +++ b/elab_expr.cc @@ -4321,12 +4321,7 @@ unsigned PEIdent::test_width(Design*des, NetScope*scope, width_mode_t&mode) const index_component_t&index_tail = name_tail.index.back(); ivl_assert(*this, index_tail.msb); } - // If we have a net in hand, then we can predict what the - // slice width will be. If not, then assume it will be a - // simple bit select. If the net only has a single dimension - // then this is still a simple bit select. - if ((sr.net == 0) || (sr.net->packed_dimensions() <= 1)) - use_width = 1; + use_width = 1; break; case index_component_t::SEL_BIT_LAST: if (debug_elaborate) {