diff --git a/Documentation/targets/tgt-sizer.rst b/Documentation/targets/tgt-sizer.rst
index 1364e3bfa..b0bd3775f 100644
--- a/Documentation/targets/tgt-sizer.rst
+++ b/Documentation/targets/tgt-sizer.rst
@@ -1,5 +1,5 @@
 
-The sizer Code Analyzer (-tvvp)
+The sizer Code Analyzer (-tsizer)
 ===============================
 
 The sizer target does not generate any code. Instead it will print statistics about the Verilog code.