From 5e139890b60fc8771991693972e2e2e5ec6bb6d7 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Tue, 30 Jan 2024 23:31:56 +0000
Subject: [PATCH] Add regression test for connecting module output port to
 array variable (issue #1001).

---
 ivtest/ivltests/br_gh1001.v     | 22 ++++++++++++++++++++++
 ivtest/regress-vvp.list         |  1 +
 ivtest/vvp_tests/br_gh1001.json |  5 +++++
 3 files changed, 28 insertions(+)
 create mode 100644 ivtest/ivltests/br_gh1001.v
 create mode 100644 ivtest/vvp_tests/br_gh1001.json

diff --git a/ivtest/ivltests/br_gh1001.v b/ivtest/ivltests/br_gh1001.v
new file mode 100644
index 000000000..8c001ca09
--- /dev/null
+++ b/ivtest/ivltests/br_gh1001.v
@@ -0,0 +1,22 @@
+module dut(output logic [7:0] op[1:0]);
+
+assign op[0] = 8'd1;
+assign op[1] = 8'd2;
+
+endmodule
+
+module test();
+
+logic [7:0] v[1:0];
+
+dut dut(v);
+
+initial begin
+  #0 $display("%b %b", v[0], v[1]);
+  if ((v[0] === 8'd1) && (v[1] === 8'd2))
+    $display("PASSED");
+  else
+    $display("FAILED");
+end
+
+endmodule
diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list
index ba46e170f..a4ea66433 100644
--- a/ivtest/regress-vvp.list
+++ b/ivtest/regress-vvp.list
@@ -31,6 +31,7 @@ br_gh710a			vvp_tests/br_gh710a.json
 br_gh710b			vvp_tests/br_gh710b.json
 br_gh710c			vvp_tests/br_gh710c.json
 br_gh939			vvp_tests/br_gh939.json
+br_gh1001			vvp_tests/br_gh1001.json
 br_gh1018			vvp_tests/br_gh1018.json
 br_gh1029			vvp_tests/br_gh1029.json
 br_gh1075a			vvp_tests/br_gh1074a.json
diff --git a/ivtest/vvp_tests/br_gh1001.json b/ivtest/vvp_tests/br_gh1001.json
new file mode 100644
index 000000000..a43b88f04
--- /dev/null
+++ b/ivtest/vvp_tests/br_gh1001.json
@@ -0,0 +1,5 @@
+{
+    "type"   : "normal",
+    "source" : "br_gh1001.v",
+    "iverilog-args" : [ "-g2009" ]
+}