diff --git a/tgt-vhdl/process.cc b/tgt-vhdl/process.cc
index b7c2e8fd4..2e1517eef 100644
--- a/tgt-vhdl/process.cc
+++ b/tgt-vhdl/process.cc
@@ -69,7 +69,7 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
    std::ostringstream ss;
    ss << "Generated from " << type << " process in "
       << ivl_scope_tname(scope) << " ("
-      << ivl_scope_file(scope) << " line "
+      << ivl_scope_file(scope) << ":"
       << ivl_scope_lineno(scope) << ")";
    vhdl_proc->set_comment(ss.str());
 
diff --git a/tgt-vhdl/scope.cc b/tgt-vhdl/scope.cc
index 6decb334e..cfd74f611 100644
--- a/tgt-vhdl/scope.cc
+++ b/tgt-vhdl/scope.cc
@@ -557,7 +557,7 @@ static void create_skeleton_entity_for(ivl_scope_t scope)
    // Build a comment to add to the entity/architecture
    ostringstream ss;
    ss << "Generated from Verilog module " << ivl_scope_tname(scope)
-      << " (" << ivl_scope_file(scope) << " line "
+      << " (" << ivl_scope_file(scope) << ":"
       << ivl_scope_lineno(scope) << ")";
    
    arch->set_comment(ss.str());