diff --git a/attributes.txt b/attributes.txt index 3649f0157..9aff0b609 100644 --- a/attributes.txt +++ b/attributes.txt @@ -51,8 +51,13 @@ warning.) * Attributes for signals (wire/reg/integer/tri/etc.) -[ none defined yet ] +(* PAD = "" *) + If this attribute is attached to a signal that happens to be a + root module port, then targets that support it will use the string + value as a list of pin assignments for the port/signal. The format + is a comma separated list of location tokens, with the format of + the token itself defined by the back-end tools in use. * Other Attributes diff --git a/parse.y b/parse.y index 2cf2a0824..d3df3d4ed 100644 --- a/parse.y +++ b/parse.y @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #if HAVE_CVS_IDENT -#ident "$Id: parse.y,v 1.181 2003/06/20 00:53:19 steve Exp $" +#ident "$Id: parse.y,v 1.182 2003/07/04 03:57:19 steve Exp $" #endif # include "config.h" @@ -1235,63 +1235,71 @@ list_of_port_declarations port_declaration_context.port_type, port_declaration_context.port_net_type, port_declaration_context.sign_flag, - port_declaration_context.range); + port_declaration_context.range, 0); delete $1; $$ = tmp; } ; port_declaration - : K_input net_type_opt signed_opt range_opt IDENTIFIER + : attribute_list_opt + K_input net_type_opt signed_opt range_opt IDENTIFIER { Module::port_t*ptmp; - ptmp = pform_module_port_reference($5, @1.text, - @1.first_line); - pform_module_define_port(@1, $5, NetNet::PINPUT, - $2, $3, $4); + ptmp = pform_module_port_reference($6, @2.text, + @2.first_line); + pform_module_define_port(@2, $6, NetNet::PINPUT, + $3, $4, $5, $1); port_declaration_context.port_type = NetNet::PINPUT; - port_declaration_context.port_net_type = $2; - port_declaration_context.sign_flag = $3; - port_declaration_context.range = $4; - delete $5; + port_declaration_context.port_net_type = $3; + port_declaration_context.sign_flag = $4; + port_declaration_context.range = $5; + delete $1; + delete $6; $$ = ptmp; } - | K_inout net_type_opt signed_opt range_opt IDENTIFIER + | attribute_list_opt + K_inout net_type_opt signed_opt range_opt IDENTIFIER { Module::port_t*ptmp; - ptmp = pform_module_port_reference($5, @1.text, - @1.first_line); - pform_module_define_port(@1, $5, NetNet::PINOUT, - $2, $3, $4); + ptmp = pform_module_port_reference($6, @2.text, + @2.first_line); + pform_module_define_port(@2, $6, NetNet::PINOUT, + $3, $4, $5, $1); port_declaration_context.port_type = NetNet::PINOUT; - port_declaration_context.port_net_type = $2; - port_declaration_context.sign_flag = $3; - port_declaration_context.range = $4; - delete $5; + port_declaration_context.port_net_type = $3; + port_declaration_context.sign_flag = $4; + port_declaration_context.range = $5; + delete $1; + delete $6; $$ = ptmp; } - | K_output net_type_opt signed_opt range_opt IDENTIFIER + | attribute_list_opt + K_output net_type_opt signed_opt range_opt IDENTIFIER { Module::port_t*ptmp; - ptmp = pform_module_port_reference($5, @1.text, - @1.first_line); - pform_module_define_port(@1, $5, NetNet::POUTPUT, - $2, $3, $4); + ptmp = pform_module_port_reference($6, @2.text, + @2.first_line); + pform_module_define_port(@2, $6, NetNet::POUTPUT, + $3, $4, $5, $1); port_declaration_context.port_type = NetNet::POUTPUT; - port_declaration_context.port_net_type = $2; - port_declaration_context.sign_flag = $3; - port_declaration_context.range = $4; - delete $5; + port_declaration_context.port_net_type = $3; + port_declaration_context.sign_flag = $4; + port_declaration_context.range = $5; + delete $1; + delete $6; $$ = ptmp; } - | K_output var_type signed_opt range_opt IDENTIFIER + | attribute_list_opt + K_output var_type signed_opt range_opt IDENTIFIER { Module::port_t*ptmp; - ptmp = pform_module_port_reference($5, @1.text, - @1.first_line); - pform_module_define_port(@1, $5, NetNet::POUTPUT, - $2, $3, $4); + ptmp = pform_module_port_reference($6, @2.text, + @2.first_line); + pform_module_define_port(@2, $6, NetNet::POUTPUT, + $3, $4, $5, $1); port_declaration_context.port_type = NetNet::POUTPUT; - port_declaration_context.port_net_type = $2; - port_declaration_context.sign_flag = $3; - port_declaration_context.range = $4; - delete $5; + port_declaration_context.port_net_type = $3; + port_declaration_context.sign_flag = $4; + port_declaration_context.range = $5; + delete $1; + delete $6; $$ = ptmp; } ; diff --git a/pform.cc b/pform.cc index d1b8c58f6..cf4b697e0 100644 --- a/pform.cc +++ b/pform.cc @@ -17,7 +17,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: pform.cc,v 1.117 2003/06/24 01:38:03 steve Exp $" +#ident "$Id: pform.cc,v 1.118 2003/07/04 03:57:19 steve Exp $" #endif # include "config.h" @@ -891,7 +891,8 @@ void pform_module_define_port(const struct vlltype&li, NetNet::PortType port_type, NetNet::Type type, bool signed_flag, - svector*range) + svector*range, + svector*attr) { hname_t name = hier_name(nm); PWire*cur = pform_cur_module->get_wire(name); @@ -921,6 +922,12 @@ void pform_module_define_port(const struct vlltype&li, cur->set_range((*range)[0], (*range)[1]); } + if (attr) { + for (unsigned idx = 0 ; idx < attr->count() ; idx += 1) { + named_pexpr_t*tmp = (*attr)[idx]; + cur->attributes[tmp->name] = tmp->parm; + } + } pform_cur_module->add_wire(cur); } @@ -1462,6 +1469,9 @@ int pform_parse(const char*path, FILE*file) /* * $Log: pform.cc,v $ + * Revision 1.118 2003/07/04 03:57:19 steve + * Allow attributes on Verilog 2001 port declarations. + * * Revision 1.117 2003/06/24 01:38:03 steve * Various warnings fixed. * diff --git a/pform.h b/pform.h index 76fdc2093..326a2d98d 100644 --- a/pform.h +++ b/pform.h @@ -19,7 +19,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ #ifdef HAVE_CVS_IDENT -#ident "$Id: pform.h,v 1.72 2003/06/20 00:53:19 steve Exp $" +#ident "$Id: pform.h,v 1.73 2003/07/04 03:57:19 steve Exp $" #endif # include "netlist.h" @@ -129,7 +129,8 @@ extern void pform_module_define_port(const struct vlltype&li, NetNet::PortType, NetNet::Type type, bool signed_flag, - svector*range); + svector*range, + svector*attr); extern Module::port_t* pform_module_port_reference(char*name, const char*file, @@ -282,6 +283,9 @@ extern void pform_dump(ostream&out, Module*mod); /* * $Log: pform.h,v $ + * Revision 1.73 2003/07/04 03:57:19 steve + * Allow attributes on Verilog 2001 port declarations. + * * Revision 1.72 2003/06/20 00:53:19 steve * Module attributes from the parser * through to elaborated form. diff --git a/tgt-fpga/fpga.txt b/tgt-fpga/fpga.txt index 21dbe1e09..e223be329 100644 --- a/tgt-fpga/fpga.txt +++ b/tgt-fpga/fpga.txt @@ -2,7 +2,7 @@ FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog Copyright 2001 Stephen Williams - $Id: fpga.txt,v 1.9 2003/07/04 01:08:03 steve Exp $ + $Id: fpga.txt,v 1.10 2003/07/04 03:57:19 steve Exp $ The FPGA code generator supports a variety of FPGA devices, writing XNF or EDIF depending on the target. You can select the architecture @@ -129,17 +129,19 @@ the value of that attribute is a list of locations, one for each bit of the signal, that specifies the pin for each bit of the signal. For example: - module main(out, in); - output out; - input [2:0] in; + module main( (* PAD = "P10" *) output out, + (* PAD = "P20,P21,P22" *) input [2:0] in); + [...] - $attribute(out, "PAD", "10"); - $attribute(in, "PAD", "20,21,22"); + endmodule In this example, port ``out'' is assigned to pin 10, and port ``in'' is assigned to pins 20-22. If the architecture supports it, a pin -number of 0 means let the back end tools choose a pin. +number of 0 means let the back end tools choose a pin. The format of +the pin number depends on the architecture family being targeted, so +for example Xilinx family devices take the name that is associated +with the "LOC" attribute. NOTE: If a module port is assigned to a pin (and therefore attached to a PAD) then it is *not* connected to a port of the EDIF file. This is @@ -179,6 +181,9 @@ Compile a single-file design with command line tools like so: --- $Log: fpga.txt,v $ +Revision 1.10 2003/07/04 03:57:19 steve + Allow attributes on Verilog 2001 port declarations. + Revision 1.9 2003/07/04 01:08:03 steve PAD attribute can be used to assign pins.