From 54afdc1e6b286159a9da0a4977029fe0f5dfcfe8 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Sat, 1 Oct 2022 13:49:10 +0200
Subject: [PATCH] Add regression test for module port with vector typedef

Check that for a module port with a vector type identifier the type is
elaborated in the scope where it is declared rather than the scope of the
module port.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 ivtest/ivltests/module_port_typedef_vector.v | 29 ++++++++++++++++++++
 ivtest/regress-sv.list                       |  1 +
 2 files changed, 30 insertions(+)
 create mode 100644 ivtest/ivltests/module_port_typedef_vector.v

diff --git a/ivtest/ivltests/module_port_typedef_vector.v b/ivtest/ivltests/module_port_typedef_vector.v
new file mode 100644
index 000000000..ca5d4592a
--- /dev/null
+++ b/ivtest/ivltests/module_port_typedef_vector.v
@@ -0,0 +1,29 @@
+// Check that a packed array type identifier used for a module port is
+// elaborated in the correct scope.
+
+localparam A = 2;
+
+typedef logic [A-1:0] T;
+
+module test (
+  input T x
+);
+
+  localparam A = 5;
+
+  bit failed = 1'b0;
+
+  `define check(expr, val) \
+    if (expr !== val) begin \
+      $display("FAILED: %s, expected %0d, got %0d", `"expr`", val, expr); \
+      failed = 1'b1; \
+    end
+
+  initial begin
+    `check($bits(x), 2);
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule
diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list
index e423c2a86..f57aba917 100644
--- a/ivtest/regress-sv.list
+++ b/ivtest/regress-sv.list
@@ -371,6 +371,7 @@ module_nonansi_struct_fail CE,-g2005-sv	ivltests
 module_output_port_sv_var1 normal,-g2005-sv	ivltests
 module_output_port_sv_var2 normal,-g2005-sv	ivltests
 module_port_typedef_array1 normal,-g2005-sv	ivltests
+module_port_typedef_vector normal,-g2005-sv	ivltests
 named_begin		normal,-g2009		ivltests
 named_begin_fail	CE,-g2009		ivltests
 named_fork		normal,-g2009		ivltests