diff --git a/vhdlpp/expression.h b/vhdlpp/expression.h
index 6f2d2b4fe..443332e85 100644
--- a/vhdlpp/expression.h
+++ b/vhdlpp/expression.h
@@ -501,7 +501,7 @@ class ExpInteger : public Expression {
       void write_to_stream(std::ostream&fd);
       int emit(ostream&out, Entity*ent, ScopeBase*scope);
       int emit_package(std::ostream&out);
-      bool is_primary(void) const;
+      bool is_primary(void) const { return true; }
       bool evaluate(ScopeBase*scope, int64_t&val) const;
       void dump(ostream&out, int indent = 0) const;
       virtual ostream& dump_inline(ostream&out) const;
diff --git a/vhdlpp/expression_emit.cc b/vhdlpp/expression_emit.cc
index 04b4d21a3..bf5d47e92 100644
--- a/vhdlpp/expression_emit.cc
+++ b/vhdlpp/expression_emit.cc
@@ -562,9 +562,9 @@ int ExpFunc::emit(ostream&out, Entity*ent, ScopeBase*scope)
 	    out << ")";
 
       } else if (name_ == "integer" && argv_.size() == 1) {
-            // Simply skip the function name, SystemVerilog takes care of
-            // rounding real numbers
+	    out << "$signed(";
 	    errors += argv_[0]->emit(out, ent, scope);
+	    out << ")";
 
       } else if (name_ == "std_logic_vector" && argv_.size() == 1) {
 	      // Special case: The std_logic_vector function casts its
@@ -635,11 +635,6 @@ int ExpInteger::emit_package(ostream&out)
       return 0;
 }
 
-bool ExpInteger::is_primary(void) const
-{
-      return true;
-}
-
 int ExpReal::emit(ostream&out, Entity*, ScopeBase*)
 {
       out << value_;