diff --git a/ivtest/ivltests/sv_class_prop_packed_dims.v b/ivtest/ivltests/sv_class_prop_packed_dims.v
new file mode 100644
index 000000000..05d97179e
--- /dev/null
+++ b/ivtest/ivltests/sv_class_prop_packed_dims.v
@@ -0,0 +1,40 @@
+// Check that multi-dimensional packed vector class properties are supported.
+
+module test;
+
+  bit failed = 1'b0;
+
+  `define check(val, exp) do begin \
+    if (val !== exp) begin \
+      $display("FAILED(%0d). '%s' expected %0h, got %0h", `__LINE__, \
+               `"val`", exp, val); \
+      failed = 1'b1; \
+    end \
+  end while (0)
+
+  class C;
+    logic [1:0][3:0] x;
+    bit [0:1][0:3] y;
+  endclass
+
+  C c;
+
+  initial begin
+    c = new;
+
+    c.x = 8'h5a;
+    c.y = 8'hc3;
+    `check(c.x, 8'h5a);
+    `check(c.y, 8'hc3);
+
+    c.x += 8'h01;
+    c.y ^= 8'hff;
+    `check(c.x, 8'h5b);
+    `check(c.y, 8'h3c);
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule
diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list
index 2475c4d3a..b562ceacc 100644
--- a/ivtest/regress-vvp.list
+++ b/ivtest/regress-vvp.list
@@ -264,6 +264,7 @@ sv_chained_constructor5		vvp_tests/sv_chained_constructor5.json
 sv_class_prop_assign_op1	vvp_tests/sv_class_prop_assign_op1.json
 sv_class_prop_assign_op2	vvp_tests/sv_class_prop_assign_op2.json
 sv_class_prop_logic		vvp_tests/sv_class_prop_logic.json
+sv_class_prop_packed_dims	vvp_tests/sv_class_prop_packed_dims.json
 sv_class_prop_nest_darray1	vvp_tests/sv_class_prop_nest_darray1.json
 sv_class_prop_nest_obj1		vvp_tests/sv_class_prop_nest_obj1.json
 sv_class_prop_nest_real1	vvp_tests/sv_class_prop_nest_real1.json
diff --git a/ivtest/vvp_tests/sv_class_prop_packed_dims.json b/ivtest/vvp_tests/sv_class_prop_packed_dims.json
new file mode 100644
index 000000000..2697dc424
--- /dev/null
+++ b/ivtest/vvp_tests/sv_class_prop_packed_dims.json
@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_class_prop_packed_dims.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment"     : "Classes are not supported",
+        "type"          : "CE"
+    }
+}
diff --git a/tgt-vvp/draw_class.c b/tgt-vvp/draw_class.c
index afbc26d5c..69431d7b6 100644
--- a/tgt-vvp/draw_class.c
+++ b/tgt-vvp/draw_class.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2012-2026 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -28,7 +28,6 @@ static void show_prop_type_vector(ivl_type_t ptype)
 {
       ivl_variable_type_t data_type = ivl_type_base(ptype);
       unsigned packed_dimensions = ivl_type_packed_dimensions(ptype);
-      assert(packed_dimensions < 2);
 
       const char*signed_flag = ivl_type_signed(ptype)? "s" : "";
       char code = data_type==IVL_VT_BOOL? 'b' : 'L';
@@ -37,12 +36,8 @@ static void show_prop_type_vector(ivl_type_t ptype)
 	    fprintf(vvp_out, "\"%s%c1\"", signed_flag, code);
 
       } else {
-	    assert(packed_dimensions == 1);
-	    assert(ivl_type_packed_lsb(ptype,0) == 0);
-	    assert(ivl_type_packed_msb(ptype,0) >= 0);
-
 	    fprintf(vvp_out, "\"%s%c%d\"", signed_flag, code,
-		    ivl_type_packed_msb(ptype,0)+1);
+		    ivl_type_packed_width(ptype));
       }
 }
 
diff --git a/tgt-vvp/stmt_assign.c b/tgt-vvp/stmt_assign.c
index ac0a92dd3..d8c2aefec 100644
--- a/tgt-vvp/stmt_assign.c
+++ b/tgt-vvp/stmt_assign.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2025 Stephen Williams (steve@icarus.com)
+ * Copyright (c) 2011-2026 Stephen Williams (steve@icarus.com)
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -1319,10 +1319,6 @@ static int show_stmt_assign_sig_cobject(ivl_statement_t net)
 
 	    if (ivl_type_base(prop_type) == IVL_VT_BOOL ||
 	        ivl_type_base(prop_type) == IVL_VT_LOGIC) {
-		  assert(ivl_type_packed_dimensions(prop_type) == 0 ||
-		         (ivl_type_packed_dimensions(prop_type) == 1 &&
-		          ivl_type_packed_msb(prop_type,0) >= ivl_type_packed_lsb(prop_type, 0)));
-
 		  if (ivl_stmt_opcode(net) != 0) {
 			fprintf(vvp_out, "    %%prop/v %d;\n", prop_idx);
 		  }