From 4ae2eec275d8cd1b8475b2be5ae55ce04af37e79 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Tue, 12 Apr 2022 18:37:34 +0200
Subject: [PATCH] Add regression test for Verilog AMS abs() with function call
 argument

Check that the behavior of the Verilog AMS `abs()` function is correct when
its argument is a function call. Check this for both vector as well as real
types.

This test is largely a copy of the existing vams_abs2 test, just replacing
the identifier argument with a function call argument.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 ivtest/ivltests/vams_abs3.v | 59 +++++++++++++++++++++++++++++++++++++
 ivtest/regress-vams.list    |  1 +
 ivtest/regress-vlog95.list  |  1 +
 3 files changed, 61 insertions(+)
 create mode 100644 ivtest/ivltests/vams_abs3.v

diff --git a/ivtest/ivltests/vams_abs3.v b/ivtest/ivltests/vams_abs3.v
new file mode 100644
index 000000000..3111f9df0
--- /dev/null
+++ b/ivtest/ivltests/vams_abs3.v
@@ -0,0 +1,59 @@
+// Check that VAMS `abs()` functions works if its argument is a function call
+
+module main;
+
+   function reg signed [7:0] fv(input reg signed [7:0] x);
+      fv = x;
+   endfunction
+
+   function real fr(input real x);
+      fr = x;
+   endfunction
+
+   reg signed [7:0]  a;
+   wire signed [7:0] vala = abs(fv(a));
+
+   reg	      real  b;
+   wire       real  valb = abs(fr(b));
+
+   initial begin
+      a = 0;
+      b = 0;
+      #1 if (vala !== 0) begin
+	 $display("FAILED -- a=%b, vala=%b", a, vala);
+	 $finish;
+      end
+
+      #1 if (valb != 0) begin
+	 $display("FAILED -- b=%g valb=%g", b, valb);
+	 $finish;
+      end
+
+      a = 1;
+      b = 1;
+      #1 if (vala !== 1) begin
+	 $display("FAILED -- a=%b, vala=%b", a, vala);
+	 $finish;
+      end
+
+      #1 if (valb != 1) begin
+	 $display("FAILED -- b=%g valb=%g", b, valb);
+	 $finish;
+      end
+
+      a = -1;
+      b = -1;
+      #1 if (vala !== 1) begin
+	 $display("FAILED -- a=%b, vala=%b", a, vala);
+	 $finish;
+      end
+
+      #1 if (valb != 1) begin
+	 $display("FAILED -- b=%g valb=%g", b, valb);
+	 $finish;
+      end
+
+      $display("PASSED");
+   end
+
+endmodule // main
diff --git a/ivtest/regress-vams.list b/ivtest/regress-vams.list
index 68c4ae5ef..35f5b2ff1 100644
--- a/ivtest/regress-vams.list
+++ b/ivtest/regress-vams.list
@@ -81,6 +81,7 @@ value_range2		normal,-gverilog-ams	ivltests
 value_range3		CE,-gverilog-ams	ivltests
 vams_abs1		normal,-gverilog-ams	ivltests
 vams_abs2		normal,-gverilog-ams	ivltests
+vams_abs3		normal,-gverilog-ams	ivltests
 wreal			normal,-gverilog-ams	ivltests
 # Verilog functions added in a VAMS simulator
 constfunc6_ams		normal			ivltests
diff --git a/ivtest/regress-vlog95.list b/ivtest/regress-vlog95.list
index b70b1bd66..c02c18ea6 100644
--- a/ivtest/regress-vlog95.list
+++ b/ivtest/regress-vlog95.list
@@ -158,6 +158,7 @@ real_wire_force_rel	CE			ivltests
 tern8			CE			ivltests
 v2005_math		CE			ivltests
 vams_abs2		CE,-gverilog-ams,-pallowsigned=1	ivltests
+vams_abs3		CE,-gverilog-ams,-pallowsigned=1	ivltests
 vhdl_real		CE,-g2009,ivltests/vhdl_real.vhd	ivltests
 vhdl_unbounded		CE,-g2009,ivltests/vhdl_unbounded.vhd	ivltests
 wreal			CE			ivltests