From 48d397229904ded352c60a53ae24c1a61127e1ac Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Fri, 24 Oct 2014 15:13:28 -0700
Subject: [PATCH] Remove a bunch of dead vvp opcodes.

---
 tgt-vvp/vvp_process.c |   44 --
 vvp/codes.h           |   21 -
 vvp/compile.cc        |   21 -
 vvp/opcodes.txt       |  171 -------
 vvp/vthread.cc        | 1120 +----------------------------------------
 5 files changed, 9 insertions(+), 1368 deletions(-)

diff --git a/tgt-vvp/vvp_process.c b/tgt-vvp/vvp_process.c
index 4183df81f..22b9ced3c 100644
--- a/tgt-vvp/vvp_process.c
+++ b/tgt-vvp/vvp_process.c
@@ -290,50 +290,7 @@ static void assign_to_lvector(ivl_lval_t lval,
 	    }
 
       } else if (part_off>0 || ivl_lval_width(lval)!=ivl_signal_width(sig)) {
-#if 0
-	      /* There is no mux expression, but a constant part
-		 offset. Load that into index x1 and generate a
-		 single-bit set instruction. */
-	    assert(ivl_lval_width(lval) == width);
 
-	    if (dexp != 0) {
-		    /* Calculated delay... */
-		  int delay_index = allocate_word();
-		  draw_eval_expr_into_integer(dexp, delay_index);
-		  fprintf(vvp_out, "    %%ix/load 0, %u, 0;\n", width);
-		  fprintf(vvp_out, "    %%ix/load 1, %lu, 0;\n", part_off);
-		  fprintf(vvp_out, "    %%assign/v0/x1/d v%p_%lu, %d, %u;\n",
-			  sig, use_word, delay_index, bit);
-		  clr_word(delay_index);
-	    } else if (nevents != 0) {
-		    /* Event control delay... */
-		  fprintf(vvp_out, "    %%ix/load 0, %u, 0;\n", width);
-		  fprintf(vvp_out, "    %%ix/load 1, %lu, 0;\n", part_off);
-		  fprintf(vvp_out, "    %%assign/v0/x1/e v%p_%lu, %u;\n",
-			  sig, use_word, bit);
-	    } else {
-		    /* Constant delay... */
-		  fprintf(vvp_out, "    %%ix/load 0, %u, 0;\n", width);
-		  fprintf(vvp_out, "    %%ix/load 1, %lu, 0;\n", part_off);
-		    /*
-		     * The %assign can only take a 32 bit delay. For a larger
-		     * delay we need to put it into an index register.
-		     */
-		  if (hig_d != 0) {
-			int delay_index = allocate_word();
-			fprintf(vvp_out, "    %%ix/load %d, %lu, %lu;\n",
-			        delay_index, low_d, hig_d);
-			fprintf(vvp_out,
-			        "    %%assign/v0/x1/d v%p_%lu, %d, %u;\n",
-			        sig, use_word, delay_index, bit);
-			clr_word(delay_index);
-		  } else {
-			fprintf(vvp_out,
-			        "    %%assign/v0/x1 v%p_%lu, %lu, %u;\n",
-			        sig, use_word, low_d, bit);
-		  }
-	    }
-#else
 	    if (nevents != 0) {
 		  assert(dexp==0);
 		  int offset_index = allocate_word();
@@ -364,7 +321,6 @@ static void assign_to_lvector(ivl_lval_t lval,
 		  clr_word(offset_index);
 		  clr_word(delay_index);
 	    }
-#endif
 
       } else if (dexp != 0) {
 	      /* Calculated delay... */
diff --git a/vvp/codes.h b/vvp/codes.h
index b74c40b95..f3c0511ff 100644
--- a/vvp/codes.h
+++ b/vvp/codes.h
@@ -34,16 +34,12 @@ typedef bool (*vvp_code_fun)(vthread_t thr, vvp_code_t code);
 extern bool of_ABS_WR(vthread_t thr, vvp_code_t code);
 extern bool of_ADD(vthread_t thr, vvp_code_t code);
 extern bool of_ADD_WR(vthread_t thr, vvp_code_t code);
-extern bool of_ADDI(vthread_t thr, vvp_code_t code);
 extern bool of_ALLOC(vthread_t thr, vvp_code_t code);
 extern bool of_AND(vthread_t thr, vvp_code_t code);
-extern bool of_ANDI(vthread_t thr, vvp_code_t code);
 extern bool of_ANDR(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_AR(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_ARD(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_ARE(vthread_t thr, vvp_code_t code);
-extern bool of_ASSIGN_AV(vthread_t thr, vvp_code_t code);
-extern bool of_ASSIGN_AVD(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_D(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_MV(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_VEC4(vthread_t thr, vvp_code_t code);
@@ -53,13 +49,9 @@ extern bool of_ASSIGN_VEC4_A_D(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_VEC4_A_E(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_VEC4_OFF_D(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_VEC4_OFF_E(vthread_t thr, vvp_code_t code);
-extern bool of_ASSIGN_V0X1(vthread_t thr, vvp_code_t code);
-extern bool of_ASSIGN_V0X1D(vthread_t thr, vvp_code_t code);
-extern bool of_ASSIGN_V0X1E(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_WR(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_WRD(vthread_t thr, vvp_code_t code);
 extern bool of_ASSIGN_WRE(vthread_t thr, vvp_code_t code);
-extern bool of_ASSIGN_X0(vthread_t thr, vvp_code_t code);
 extern bool of_BLEND(vthread_t thr, vvp_code_t code);
 extern bool of_BLEND_WR(vthread_t thr, vvp_code_t code);
 extern bool of_BREAKPOINT(vthread_t thr, vvp_code_t code);
@@ -68,8 +60,6 @@ extern bool of_CASSIGN_VEC4(vthread_t thr, vvp_code_t code);
 extern bool of_CASSIGN_VEC4_OFF(vthread_t thr, vvp_code_t code);
 extern bool of_CASSIGN_WR(vthread_t thr, vvp_code_t code);
 extern bool of_CAST2(vthread_t thr, vvp_code_t code);
-extern bool of_CMPIS(vthread_t thr, vvp_code_t code);
-extern bool of_CMPIU(vthread_t thr, vvp_code_t code);
 extern bool of_CMPS(vthread_t thr, vvp_code_t code);
 extern bool of_CMPSTR(vthread_t thr, vvp_code_t code);
 extern bool of_CMPU(vthread_t thr, vvp_code_t code);
@@ -137,10 +127,6 @@ extern bool of_JMP1XZ(vthread_t thr, vvp_code_t code);
 extern bool of_JOIN(vthread_t thr, vvp_code_t code);
 extern bool of_JOIN_DETACH(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_AR(vthread_t thr, vvp_code_t code);
-extern bool of_LOAD_AV(vthread_t thr, vvp_code_t code);
-extern bool of_LOAD_AVP0(vthread_t thr, vvp_code_t code);
-extern bool of_LOAD_AVP0_S(vthread_t thr, vvp_code_t code);
-extern bool of_LOAD_AVX_P(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_REAL(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_DAR_R(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_DAR_STR(vthread_t thr, vvp_code_t code);
@@ -153,18 +139,14 @@ extern bool of_LOAD_VEC4(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_VEC4A(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_VP0(vthread_t thr, vvp_code_t code);
 extern bool of_LOAD_VP0_S(vthread_t thr, vvp_code_t code);
-extern bool of_LOAD_X1P(vthread_t thr, vvp_code_t code);
 extern bool of_MAX_WR(vthread_t thr, vvp_code_t code);
 extern bool of_MIN_WR(vthread_t thr, vvp_code_t code);
 extern bool of_MOD(vthread_t thr, vvp_code_t code);
 extern bool of_MOD_S(vthread_t thr, vvp_code_t code);
 extern bool of_MOD_WR(vthread_t thr, vvp_code_t code);
-extern bool of_MOV(vthread_t thr, vvp_code_t code);
 extern bool of_MOV_WU(vthread_t thr, vvp_code_t code);
-extern bool of_MOVI(vthread_t thr, vvp_code_t code);
 extern bool of_MUL(vthread_t thr, vvp_code_t code);
 extern bool of_MUL_WR(vthread_t thr, vvp_code_t code);
-extern bool of_MULI(vthread_t thr, vvp_code_t code);
 extern bool of_NAND(vthread_t thr, vvp_code_t code);
 extern bool of_NANDR(vthread_t thr, vvp_code_t code);
 extern bool of_NEW_COBJ(vthread_t thr, vvp_code_t code);
@@ -204,13 +186,11 @@ extern bool of_RELEASE_REG(vthread_t thr, vvp_code_t code);
 extern bool of_RELEASE_WR(vthread_t thr, vvp_code_t code);
 extern bool of_REPLICATE(vthread_t thr, vvp_code_t code);
 extern bool of_SCOPY(vthread_t thr, vvp_code_t code);
-extern bool of_SET_AV(vthread_t thr, vvp_code_t code);
 extern bool of_SET_QB(vthread_t thr, vvp_code_t code);
 extern bool of_SET_QF(vthread_t thr, vvp_code_t code);
 extern bool of_SET_DAR_OBJ_REAL(vthread_t thr, vvp_code_t code);
 extern bool of_SET_DAR_OBJ_STR(vthread_t thr, vvp_code_t code);
 extern bool of_SET_DAR_OBJ_VEC4(vthread_t thr, vvp_code_t code);
-extern bool of_SET_X0(vthread_t thr, vvp_code_t code);
 extern bool of_SET_X0_X(vthread_t thr, vvp_code_t code);
 extern bool of_SHIFTL(vthread_t thr, vvp_code_t code);
 extern bool of_SHIFTR(vthread_t thr, vvp_code_t code);
@@ -239,7 +219,6 @@ extern bool of_STORE_VEC4(vthread_t thr, vvp_code_t code);
 extern bool of_STORE_VEC4A(vthread_t thr, vvp_code_t code);
 extern bool of_SUB(vthread_t thr, vvp_code_t code);
 extern bool of_SUB_WR(vthread_t thr, vvp_code_t code);
-extern bool of_SUBI(vthread_t thr, vvp_code_t code);
 extern bool of_SUBSTR(vthread_t thr, vvp_code_t code);
 extern bool of_SUBSTR_VEC4(vthread_t thr, vvp_code_t code);
 extern bool of_TEST_NUL(vthread_t thr, vvp_code_t code);
diff --git a/vvp/compile.cc b/vvp/compile.cc
index fd38da18a..989a0f645 100644
--- a/vvp/compile.cc
+++ b/vvp/compile.cc
@@ -87,19 +87,12 @@ static const struct opcode_table_s opcode_table[] = {
       { "%abs/wr", of_ABS_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%add",    of_ADD,    0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%add/wr", of_ADD_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%addi",   of_ADDI,   3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%alloc",  of_ALLOC,  1,  {OA_VPI_PTR,  OA_NONE,     OA_NONE} },
       { "%and",    of_AND,    0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%and/r",  of_ANDR,   0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%andi",   of_ANDI,   3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%assign/ar",of_ASSIGN_AR,2,{OA_ARR_PTR,OA_BIT1,     OA_NONE} },
       { "%assign/ar/d",of_ASSIGN_ARD,2,{OA_ARR_PTR,OA_BIT1,  OA_NONE} },
       { "%assign/ar/e",of_ASSIGN_ARE,1,{OA_ARR_PTR,OA_NONE,  OA_NONE} },
-      { "%assign/av",of_ASSIGN_AV,3,{OA_ARR_PTR,OA_BIT1,     OA_BIT2} },
-      { "%assign/av/d",of_ASSIGN_AVD,3,{OA_ARR_PTR,OA_BIT1,  OA_BIT2} },
-      { "%assign/v0/x1",of_ASSIGN_V0X1,3,{OA_FUNC_PTR,OA_BIT1,OA_BIT2} },
-      { "%assign/v0/x1/d",of_ASSIGN_V0X1D,3,{OA_FUNC_PTR,OA_BIT1,OA_BIT2} },
-      { "%assign/v0/x1/e",of_ASSIGN_V0X1E,2,{OA_FUNC_PTR,OA_BIT1,OA_NONE} },
       { "%assign/vec4",      of_ASSIGN_VEC4,       2, {OA_FUNC_PTR, OA_BIT1, OA_NONE} },
       { "%assign/vec4/a/d",  of_ASSIGN_VEC4_A_D,   3, {OA_ARR_PTR,  OA_BIT1, OA_BIT2} },
       { "%assign/vec4/a/e",  of_ASSIGN_VEC4_A_E,   2, {OA_ARR_PTR,  OA_BIT1, OA_NONE} },
@@ -110,7 +103,6 @@ static const struct opcode_table_s opcode_table[] = {
       { "%assign/wr",  of_ASSIGN_WR, 2,{OA_VPI_PTR, OA_BIT1, OA_NONE} },
       { "%assign/wr/d",of_ASSIGN_WRD,2,{OA_VPI_PTR, OA_BIT1, OA_NONE} },
       { "%assign/wr/e",of_ASSIGN_WRE,1,{OA_VPI_PTR, OA_NONE, OA_NONE} },
-      { "%assign/x0",of_ASSIGN_X0,3,{OA_FUNC_PTR,OA_BIT1,    OA_BIT2} },
       { "%blend",    of_BLEND,   0,  {OA_NONE,  OA_NONE,     OA_NONE} },
       { "%blend/wr", of_BLEND_WR,0,  {OA_NONE,  OA_NONE,     OA_NONE} },
       { "%breakpoint", of_BREAKPOINT, 0,  {OA_NONE, OA_NONE, OA_NONE} },
@@ -127,8 +119,6 @@ static const struct opcode_table_s opcode_table[] = {
       { "%cmp/wu", of_CMPWU,  2,  {OA_BIT1,     OA_BIT2,     OA_NONE} },
       { "%cmp/x",  of_CMPX,   0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%cmp/z",  of_CMPZ,   0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%cmpi/s", of_CMPIS,  3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
-      { "%cmpi/u", of_CMPIU,  3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%concat/str", of_CONCAT_STR, 0,{OA_NONE,  OA_NONE,  OA_NONE} },
       { "%concat/vec4",of_CONCAT_VEC4,0,{OA_NONE,  OA_NONE,  OA_NONE} },
       { "%concati/str",of_CONCATI_STR,1,{OA_STRING,OA_NONE,  OA_NONE} },
@@ -185,10 +175,6 @@ static const struct opcode_table_s opcode_table[] = {
       { "%join",   of_JOIN,   0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%join/detach",of_JOIN_DETACH,1,{OA_NUMBER,OA_NONE,  OA_NONE} },
       { "%load/ar",of_LOAD_AR,2,  {OA_ARR_PTR,  OA_BIT1,     OA_NONE} },
-      { "%load/av",of_LOAD_AV,3,  {OA_BIT1,     OA_ARR_PTR,  OA_BIT2} },
-      { "%load/avp0",of_LOAD_AVP0,3,  {OA_BIT1, OA_ARR_PTR,  OA_BIT2} },
-      { "%load/avp0/s",of_LOAD_AVP0_S,3,{OA_BIT1,OA_ARR_PTR, OA_BIT2} },
-      { "%load/avx.p",of_LOAD_AVX_P,3,{OA_BIT1, OA_ARR_PTR,  OA_BIT2} },
       { "%load/dar/r",  of_LOAD_DAR_R,    1, {OA_FUNC_PTR, OA_NONE, OA_NONE}},
       { "%load/dar/str",of_LOAD_DAR_STR,  1, {OA_FUNC_PTR, OA_NONE, OA_NONE} },
       { "%load/dar/vec4",of_LOAD_DAR_VEC4,1, {OA_FUNC_PTR, OA_NONE, OA_NONE} },
@@ -201,18 +187,14 @@ static const struct opcode_table_s opcode_table[] = {
       { "%load/vec4a", of_LOAD_VEC4A,2,{OA_ARR_PTR, OA_BIT1, OA_NONE} },
       { "%load/vp0",of_LOAD_VP0,3,{OA_BIT1,     OA_FUNC_PTR, OA_BIT2} },
       { "%load/vp0/s",of_LOAD_VP0_S,3,{OA_BIT1,     OA_FUNC_PTR, OA_BIT2} },
-      { "%load/x1p",of_LOAD_X1P,3,{OA_BIT1,     OA_FUNC_PTR, OA_BIT2} },
       { "%max/wr", of_MAX_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%min/wr", of_MIN_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%mod",    of_MOD,    0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%mod/s",  of_MOD_S,  0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%mod/wr", of_MOD_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%mov",    of_MOV,    3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%mov/wu", of_MOV_WU, 2,  {OA_BIT1,     OA_BIT2,     OA_NONE} },
-      { "%movi",   of_MOVI,   3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%mul",    of_MUL,    0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%mul/wr", of_MUL_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%muli",   of_MULI,   3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%nand",   of_NAND,   0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%nand/r", of_NANDR,  0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%new/cobj",  of_NEW_COBJ,  1, {OA_VPI_PTR,OA_NONE,  OA_NONE} },
@@ -252,13 +234,11 @@ static const struct opcode_table_s opcode_table[] = {
       { "%release/wr", of_RELEASE_WR, 2,{OA_FUNC_PTR,OA_BIT1,OA_NONE} },
       { "%replicate", of_REPLICATE,   1,{OA_NUMBER,  OA_NONE,OA_NONE} },
       { "%scopy",  of_SCOPY,  0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%set/av", of_SET_AV, 3,  {OA_ARR_PTR,  OA_BIT1,     OA_BIT2} },
       { "%set/dar/obj/real",of_SET_DAR_OBJ_REAL,1,{OA_NUMBER,OA_NONE,OA_NONE} },
       { "%set/dar/obj/str", of_SET_DAR_OBJ_STR, 1,{OA_NUMBER,OA_NONE,OA_NONE} },
       { "%set/dar/obj/vec4",of_SET_DAR_OBJ_VEC4,1,{OA_NUMBER,OA_NONE,OA_NONE} },
       { "%set/qb", of_SET_QB, 3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
       { "%set/qf", of_SET_QF, 3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
-      { "%set/x0", of_SET_X0, 3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
       { "%shiftl",   of_SHIFTL,   1, {OA_NUMBER, OA_NONE,   OA_NONE} },
       { "%shiftr",   of_SHIFTR,   1, {OA_NUMBER, OA_NONE,   OA_NONE} },
       { "%shiftr/s", of_SHIFTR_S, 1, {OA_NUMBER, OA_NONE,   OA_NONE} },
@@ -286,7 +266,6 @@ static const struct opcode_table_s opcode_table[] = {
       { "%store/vec4a",   of_STORE_VEC4A,   3, {OA_ARR_PTR, OA_BIT1, OA_BIT2} },
       { "%sub",    of_SUB,    0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%sub/wr", of_SUB_WR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },
-      { "%subi",   of_SUBI,   3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%substr",     of_SUBSTR,     2,{OA_BIT1,    OA_BIT2, OA_NONE} },
       { "%substr/vec4",of_SUBSTR_VEC4,2,{OA_BIT1,    OA_BIT2, OA_NONE} },
       { "%test_nul",     of_TEST_NUL,     1,{OA_FUNC_PTR,OA_NONE,    OA_NONE} },
diff --git a/vvp/opcodes.txt b/vvp/opcodes.txt
index c7c71a619..95d005cb7 100644
--- a/vvp/opcodes.txt
+++ b/vvp/opcodes.txt
@@ -69,13 +69,6 @@ pushed in place
 
 See also the %sub/wr instruction.
 
-
-* %addi <bit-l>, <imm>, <wid>
-
-This instruction adds the immediate value (no x or z bits) into the
-left vector. The imm value is limited to 16 significant bits, but it
-is zero extended to match any width.
-
 * %alloc <scope-label>
 
 This instruction allocates the storage for a new instance of an
@@ -120,31 +113,6 @@ The %assign/ar/e variation uses the information in the thread
 event control registers to determine when to perform the assign.
 %evctl is used to set the event control information.
 
-* %assign/av <array-label>, <delay>, <bit> (XXXX Old definition)
-* %assign/av/d <array-label>, <delayx>, <bit> (XXXX Old definition)
-* %assign/av/e <array-label>, <bit> (XXXX Old definition)
-
-The %assign/av instruction assigns a vector value to a word in the
-labeled array. The <delay> is the delay in simulation time to the
-assignment (0 for non-blocking assignment) and the <bit> is the base
-of the vector to write.
-
-The width of the vector is retrieved from index register 0.
-
-The base of a part select is retrieved from index register 1.
-
-The address of the word in the memory is from index register 3. The
-address is canonical form.
-
-The %assign/av/d variation reads the delay from an integer register that
-is given by the <delayx> value. This should not be 0, 1 or 3, of course,
-since these registers contain the vector width, base part select and
-word address.
-
-The %assign/av/e variation uses the information in the thread
-event control registers to determine when to perform the assign.
-%evctl is used to set the event control information.
-
 * %assign/v0 <var-label>, <delay>, <bit> (XXXX Old description)
 * %assign/v0/d <var-label>, <delayx>, <bit> (XXXX Old description
 * %assign/v0/e <var-label>, <bit> (XXXX Old description)
@@ -166,14 +134,6 @@ event control registers to determine when to perform the assign.
 The <var-label> references a .var object that can receive non-blocking
 assignments. For blocking assignments, see %set/v.
 
-* %assign/v0/x1 <var-label>, <delay>, <bit>
-* %assign/v0/x1/d <var-label>, <delayx>, <bit>
-* %assign/v0/x1/e <var-label>, <bit>
-
-This is similar to the %assign/v0 instruction, but adds the index-1
-index register with the canonical index of the destination where the
-vector is to be written. This allows for part writes into the vector.
-
 * %assign/vec4 <var-label>, <delay>
 * %assign/vec4/d <var-label>, <delayx>
 * %assign/vec4/e <var-label>
@@ -230,19 +190,6 @@ The %assign/wr/e variation uses the information in the thread
 event control registers to determine when to perform the assign.
 %evctl is used to set the event control information.
 
-* %assign/x0 <var-label>, <delay>, <bit> (OBSOLETE -- See %assign/v0x)
-
-This does a non-blocking assignment to a functor, similar to the
-%assign instruction. The <var-label> identifies the base functor of
-the affected variable, and the <delay> gives the delay when the
-assignment takes place. The delay may be 0. The actual functor used is
-calculated by using <var-label> as a base, and indexing with the
-index[0] index register. This supports indexed assignment.
-
-The <bit> is the address of the thread register that contains the bit
-value to assign.
-
-
 * %blend
 
 This instruction blends the bits of two vectors into a result in a
@@ -344,13 +291,6 @@ The results of the comparison go into flags 4, 5, 6 and 7:
 	5: lt  (less than)
 	6: eeq (case equal)
 
-* %cmpi/s <bit-l>, <immr>, <wid>
-* %cmpi/u <bit-l>, <immr>, <wid>
-
-These instructions are similar to the %cmp instructions above, except
-that the right hand operand is an immediate value. This is a positive
-number that the vector is compared with.
-
 * %cmp/wr
 
 Compare real values for equality and less-then. This opcode pops to
@@ -715,43 +655,6 @@ the children, and none of those children may be automatic. This
 instruction is used to implement join_none and join_any from the
 Verilog source.
 
-* %load/av <bit>, <array-label>, <wid>
-
-This instruction loads a word from the specified array. The word
-address is in index register 3. Like %load/v below the width does
-not have to match the width of the array word. See the %load/v
-description for more information.
-
-* %load/avp0 <bit>, <array-label>, <wid>
-* %load/avp0/s <bit>, <array-label>, <wid>
-
-This instruction is a mix of %load/av and %load/vp0. It loads an array
-value like %load/av and then adds a value from index register 0 to the
-result like %load/vp0. The loaded value is zero-extended to <wid>,
-then added arithmetically to the signed index register 0. The result
-is then stored in <bit>.
-
-The %load/avp0/s instruction is the same, except that the loaded
-vector is sign extended (instead of 0-extended) before the addition.
-
-* %load/avx.p <bit>, <array-label>, <index>
-
-This instruction is similar to %load/av, but it loads only a single
-bit, and the <index> is the selector for the bit to use. If <index> is
-out of range, then x is loaded. The index value is incremented by one
-if it is defined (bit 4 is not 1).
-
-* %load/dar <bit>, <functor-label>, <wid> (XXXX Old implementation)
-
-This instruction loads an array word from a dynamic array. The
-<label> refers to the variable object, and the <bit>/<wid> are the
-location in local vector space where the extracted word goes. The
-index is implicitly extracted from index register 3.
-
-The dar/r variant reads a real-value into a real-valued register.
-
-(See also %set/dar)
-
 * %load/obj <var-label>
 
 This instruction loads an object handle and pushes it to the top of
@@ -824,23 +727,6 @@ The %load/ar instruction reads a real value from an array. The <index>
 is the index register that contains the canonical word address into
 the array.
 
-* %load/x1p <bit>, <functor-label>, <wid>
-
-This is an indexed load. It uses the contents of index register 1 to
-select a part from a vector functor at <functor-label>. The
-part is pulled from the indexed bit of the addressed functor and loaded
-into the destination thread bit. The <wid> is the width of the
-part. If any bit of the desired value is outside the vector, then that
-bit is set to X.
-
-The index register 1 is interpreted as a signed value. Even though the
-address is canonical (from 0 to the width of the signal) the value in
-index register 1 may be <0 or >=wid. The load instruction handles
-filling in the out-of-bounds bits with x.
-
-When the operation is done, the <wid> is added to index register 1, to
-provide a basic auto-increment behavior.
-
 * %loadi/wr <bit>, <mant>, <exp>
 
 This opcode loads an immediate value, floating point, into the word
@@ -874,19 +760,7 @@ The /s form does signed %.
 
 This opcode is the real-valued modulus of the two real values.
 
-* %mov <dst>, <src>, <wid>
 * %mov/wu <dst>, <src>
-* %movi <dst>, <value>, <wid>
-
-This instruction copies a vector from one place in register space to
-another. The destination and source vectors are assumed to be the same
-width and non-overlapping. The <dst> may not be 0-3, but if the <src>
-is one of the 4 constant bits, the effect is to replicate the value
-into the destination vector. This is useful for filling a vector.
-
-The %movi variant moves a binary value, LSB first, into the
-destination vector. The immediate value is up to 32bits, padded with
-zeros to fill out the width.
 
 * %mul
 
@@ -901,13 +775,6 @@ result is pushed back on the vec4 stack.
 
 This opcode multiplies two real words together.
 
-
-* %muli <bit-l>, <imm>, <wid>
-
-This instruction is the same as %mul, but the second operand is an
-immediate value that is padded to the width of the result.
-
-
 * %nand
 
 Perform the bitwise NAND of two vec4 vectors, and push the result. Each
@@ -1161,41 +1028,12 @@ register that contains the LSB of the vector, and the <wid> is the
 size of the vector. The width must exactly match the width of the
 signal.
 
-* %set/av <array-label>, <bit>, <wid> (XXXX Old definition)
-
-This sets a thread vector to an array word. The <array-label>
-addresses an array device, and the <bit>,<wid> describe a vector to be
-written. Index register 3 contains the address of the word within the
-array.
-
-The base of a part select is retrieved from index register 1. The
-width is implied from the <wid> that is the argument. This is the part
-*within* the word.
-
-The address (in canonical form) is precalculated and loaded into index
-register 3. This is the address of the word within the array.
-
 * %set/qb <var-label>, <bit>, <wid>
 * %set/qf <var-label>, <bit>, <wid>
 
 This sets the vector value into the back (qb) or front (qf) of a queue
 variable.
 
-* %set/x0 <var-label>, <bit>, <wid>
-
-This sets the part of a signal vector, the address calculated by
-using the index register 0 to index the base within the vector of
-<var-label>. The destination must be a signal of some sort. Otherwise,
-the instruction will fail.
-
-The addressing is canonical (0-based) so the compiler must figure out
-non-zero offsets, if any. The width is the width of the part being
-written. The other bits of the vector are not touched.
-
-The index may be signed, and if less than 0, the beginning bits are
-not assigned. Also, if the bits go beyond the end of the signal, those
-bits are not written anywhere.
-
 * %shiftl <idx>
 * %shiftr <idx>
 * %shiftr/s <idx>
@@ -1327,15 +1165,6 @@ from the left, and the result pushed.
 
 See also the %add instruction.
 
-* %subi <bit-l>, <imm>, <wid>
-
-This instruction arithmetically subtracts the immediate value from the
-left vector. The <imm> value is a 16bit unsigned value zero-extended to
-the <wid> of the left vector. The result replaces the left vector.
-
-See also the %addi instruction.
-
-
 * %sub/wr
 
 This instruction operates on real values in word registers. The right
diff --git a/vvp/vthread.cc b/vvp/vthread.cc
index 188b95a91..0e10500b6 100644
--- a/vvp/vthread.cc
+++ b/vvp/vthread.cc
@@ -894,69 +894,6 @@ bool of_AND(vthread_t thr, vvp_code_t)
       return true;
 }
 
-
-bool of_ANDI(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned idx1 = cp->bit_idx[0];
-      unsigned long imm = cp->bit_idx[1];
-      unsigned wid = cp->number;
-
-      assert(idx1 >= 4);
-
-      vvp_vector4_t val = vthread_bits_to_vector(thr, idx1, wid);
-      vvp_vector4_t imv (wid, BIT4_0);
-
-      unsigned trans = wid;
-      if (trans > CPU_WORD_BITS)
-	    trans = CPU_WORD_BITS;
-      imv.setarray(0, trans, &imm);
-
-      val &= imv;
-
-      thr->bits4.set_vec(idx1, val);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%andi ...\n");
-#endif
-      return true;
-}
-
-#if 0
-bool of_ADD(vthread_t thr, vvp_code_t cp)
-{
-      assert(cp->bit_idx[0] >= 4);
-
-      unsigned long*lva = vector_to_array(thr, cp->bit_idx[0], cp->number);
-      unsigned long*lvb = vector_to_array(thr, cp->bit_idx[1], cp->number);
-      if (lva == 0 || lvb == 0)
-	    goto x_out;
-
-      unsigned long carry;
-      carry = 0;
-      for (unsigned idx = 0 ;  (idx*CPU_WORD_BITS) < cp->number ;  idx += 1)
-	    lva[idx] = add_with_carry(lva[idx], lvb[idx], carry);
-
-	/* We know from the vector_to_array that the address is valid
-	   in the thr->bitr4 vector, so just do the set bit. */
-
-      thr->bits4.setarray(cp->bit_idx[0], cp->number, lva);
-
-      delete[]lva;
-      delete[]lvb;
-
-      return true;
-
- x_out:
-      delete[]lva;
-      delete[]lvb;
-
-      vvp_vector4_t tmp(cp->number, BIT4_X);
-      thr->bits4.set_vec(cp->bit_idx[0], tmp);
-
-      return true;
-}
-#endif
-
 bool of_ADD(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t r = thr->pop_vec4();
@@ -1000,56 +937,6 @@ bool of_ADD_WR(vthread_t thr, vvp_code_t)
       return true;
 }
 
-/*
- * This is %addi, add-immediate. The first value is a vector, the
- * second value is the immediate value in the bin_idx[1] position. The
- * immediate value can be up to 16 bits, which are then padded to the
- * width of the vector with zero.
- */
-bool of_ADDI(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-	// Collect arguments
-      unsigned bit_addr       = cp->bit_idx[0];
-      unsigned long imm_value = cp->bit_idx[1];
-      unsigned bit_width      = cp->number;
-
-      assert(bit_addr >= 4);
-
-      unsigned word_count = (bit_width+CPU_WORD_BITS-1)/CPU_WORD_BITS;
-
-      unsigned long*lva = vector_to_array(thr, bit_addr, bit_width);
-      if (lva == 0)
-	    goto x_out;
-
-
-      unsigned long carry;
-      carry = 0;
-      for (unsigned idx = 0 ;  idx < word_count ;  idx += 1) {
-	    lva[idx] = add_with_carry(lva[idx], imm_value, carry);
-	    imm_value = 0;
-      }
-
-	/* We know from the vector_to_array that the address is valid
-	   in the thr->bitr4 vector, so just do the set bit. */
-
-      thr->bits4.setarray(bit_addr, bit_width, lva);
-
-      delete[]lva;
-
-      return true;
-
- x_out:
-      delete[]lva;
-
-      vvp_vector4_t tmp (bit_width, BIT4_X);
-      thr->bits4.set_vec(bit_addr, tmp);
-#else
-      fprintf(stderr, "XXXX NOT IMLEMENTED: %%addi ...\n");
-#endif
-      return true;
-}
-
 /* %assign/ar <array>, <delay>
  * Generate an assignment event to a real array. Index register 3
  * contains the canonical address of the word in the memory. <delay>
@@ -1111,156 +998,6 @@ bool of_ASSIGN_ARE(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-/* %assign/av <array>, <delay>, <bit>
- * This generates an assignment event to an array. Index register 0
- * contains the width of the vector (and the word) and index register
- * 3 contains the canonical address of the word in memory.
- */
-bool of_ASSIGN_AV(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = thr->words[0].w_int;
-      long off = thr->words[1].w_int;
-      long adr = thr->words[3].w_int;
-      unsigned delay = cp->bit_idx[0];
-      unsigned bit = cp->bit_idx[1];
-
-      if (adr < 0) return true;
-
-      long vwidth = get_array_word_size(cp->array);
-	// We fell off the MSB end.
-      if (off >= vwidth) return true;
-	// Trim the bits after the MSB
-      if (off + (long)wid > vwidth) {
-	    wid += vwidth - off - wid;
-      } else if (off < 0 ) {
-	      // We fell off the LSB end.
-	    if ((unsigned)-off > wid ) return true;
-	      // Trim the bits before the LSB
-	    wid += off;
-	    bit -= off;
-	    off = 0;
-      }
-
-      assert(wid > 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-
-      schedule_assign_array_word(cp->array, adr, off, value, delay);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%assign/av ...\n");
-#endif
-      return true;
-}
-
-/* %assign/av/d <array>, <delay_idx>, <bit>
- * This generates an assignment event to an array. Index register 0
- * contains the width of the vector (and the word) and index register
- * 3 contains the canonical address of the word in memory. The named
- * index register contains the delay.
- */
-bool of_ASSIGN_AVD(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = thr->words[0].w_int;
-      long off = thr->words[1].w_int;
-      long adr = thr->words[3].w_int;
-      vvp_time64_t delay = thr->words[cp->bit_idx[0]].w_uint;
-      unsigned bit = cp->bit_idx[1];
-
-      if (adr < 0) return true;
-
-      long vwidth = get_array_word_size(cp->array);
-	// We fell off the MSB end.
-      if (off >= vwidth) return true;
-	// Trim the bits after the MSB
-      if (off + (long)wid > vwidth) {
-	    wid += vwidth - off - wid;
-      } else if (off < 0 ) {
-	      // We fell off the LSB end.
-	    if ((unsigned)-off > wid ) return true;
-	      // Trim the bits before the LSB
-	    wid += off;
-	    bit -= off;
-	    off = 0;
-      }
-
-      assert(wid > 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-
-      schedule_assign_array_word(cp->array, adr, off, value, delay);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED %%assign/av/d ...\n");
-#endif
-      return true;
-}
-
-#if 0
-bool of_ASSIGN_AVE(vthread_t thr, vvp_code_t cp)
-{
-      unsigned wid = thr->words[0].w_int;
-      long off = thr->words[1].w_int;
-      long adr = thr->words[3].w_int;
-      unsigned bit = cp->bit_idx[0];
-
-      if (adr < 0) return true;
-
-      long vwidth = get_array_word_size(cp->array);
-	// We fell off the MSB end.
-      if (off >= vwidth) return true;
-	// Trim the bits after the MSB
-      if (off + (long)wid > vwidth) {
-	    wid += vwidth - off - wid;
-      } else if (off < 0 ) {
-	      // We fell off the LSB end.
-	    if ((unsigned)-off > wid ) return true;
-	      // Trim the bits before the LSB
-	    wid += off;
-	    bit -= off;
-	    off = 0;
-      }
-
-      assert(wid > 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-	// If the count is zero then just put the value.
-      if (thr->ecount == 0) {
-	    schedule_assign_array_word(cp->array, adr, off, value, 0);
-      } else {
-	    schedule_evctl(cp->array, adr, value, off, thr->event, thr->ecount);
-      }
-
-      return true;
-}
-#endif
-
-#if 0
-/*
- * This is %assign/v0 <label>, <delay>, <bit>
- * Index register 0 contains a vector width.
- */
-bool of_ASSIGN_V0(vthread_t thr, vvp_code_t cp)
-{
-      unsigned wid = thr->words[0].w_int;
-      assert(wid > 0);
-      unsigned delay = cp->bit_idx[0];
-      unsigned bit = cp->bit_idx[1];
-
-      vvp_net_ptr_t ptr (cp->net, 0);
-      if (bit >= 4) {
-	      // If the vector is not a synthetic one, then have the
-	      // scheduler pluck it directly out of my vector space.
-	    schedule_assign_plucked_vector(ptr, delay, thr->bits4, bit, wid);
-      } else {
-	    vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-	    schedule_assign_plucked_vector(ptr, delay, value, 0, wid);
-      }
-
-      return true;
-}
-#endif
-
 /*
  * %assign/vec4 <var>, <delay>
  */
@@ -1457,60 +1194,6 @@ bool of_ASSIGN_VEC4_OFF_E(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-#if 0
-/*
- * This is %assign/v0/d <label>, <delay_idx>, <bit>
- * Index register 0 contains a vector width, and the named index
- * register contains the delay.
- */
-bool of_ASSIGN_V0D(vthread_t thr, vvp_code_t cp)
-{
-      unsigned wid = thr->words[0].w_int;
-      assert(wid > 0);
-
-      vvp_time64_t delay = thr->words[cp->bit_idx[0]].w_uint;
-      unsigned bit = cp->bit_idx[1];
-
-      vvp_net_ptr_t ptr (cp->net, 0);
-      if (bit >= 4) {
-	    schedule_assign_plucked_vector(ptr, delay, thr->bits4, bit, wid);
-      } else {
-	    vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-	    schedule_assign_plucked_vector(ptr, delay, value, 0, wid);
-      }
-
-      return true;
-}
-#endif
-#if 0
-/*
- * This is %assign/v0/e <label>, <bit>
- * Index register 0 contains a vector width.
- */
-bool of_ASSIGN_V0E(vthread_t thr, vvp_code_t cp)
-{
-      assert(thr->event != 0);
-      unsigned wid = thr->words[0].w_int;
-      assert(wid > 0);
-      unsigned bit = cp->bit_idx[0];
-
-      vvp_net_ptr_t ptr (cp->net, 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-	// If the count is zero then just put the value.
-      if (thr->ecount == 0) {
-	    schedule_assign_plucked_vector(ptr, 0, value, 0, wid);
-      } else {
-	    schedule_evctl(ptr, value, 0, 0, thr->event, thr->ecount);
-      }
-
-      thr->event = 0;
-      thr->ecount = 0;
-
-      return true;
-}
-#endif
-
 /*
  * %assign/vec4/d <var-label> <delay>
  */
@@ -1552,138 +1235,6 @@ bool of_ASSIGN_VEC4E(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-/*
- * This is %assign/v0/x1 <label>, <delay>, <bit>
- * Index register 0 contains a vector part width.
- * Index register 1 contains the offset into the destination vector.
- */
-bool of_ASSIGN_V0X1(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = thr->words[0].w_int;
-      long off = thr->words[1].w_int;
-      unsigned delay = cp->bit_idx[0];
-      unsigned bit = cp->bit_idx[1];
-
-      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (cp->net->fil);
-      assert(sig);
-
-	// We fell off the MSB end.
-      if (off >= (long)sig->value_size()) return true;
-      else if (off < 0 ) {
-	      // We fell off the LSB end.
-	    if ((unsigned)-off >= wid ) return true;
-	      // Trim the bits before the LSB
-	    wid += off;
-	    bit -= off;
-	    off = 0;
-      }
-
-      assert(wid > 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-
-      vvp_net_ptr_t ptr (cp->net, 0);
-      schedule_assign_vector(ptr, off, sig->value_size(), value, delay);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%assign/v0/x1 ...\n");
-#endif
-      return true;
-}
-
-/*
- * This is %assign/v0/x1/d <label>, <delayx>, <bit>
- * Index register 0 contains a vector part width.
- * Index register 1 contains the offset into the destination vector.
- */
-bool of_ASSIGN_V0X1D(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = thr->words[0].w_int;
-      long off = thr->words[1].w_int;
-      vvp_time64_t delay = thr->words[cp->bit_idx[0]].w_uint;
-      unsigned bit = cp->bit_idx[1];
-
-      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (cp->net->fil);
-      assert(sig);
-
-	// We fell off the MSB end.
-      if (off >= (long)sig->value_size()) return true;
-      else if (off < 0 ) {
-	      // We fell off the LSB end.
-	    if ((unsigned)-off >= wid ) return true;
-	      // Trim the bits before the LSB
-	    wid += off;
-	    bit -= off;
-	    off = 0;
-      }
-
-      assert(wid > 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-
-      vvp_net_ptr_t ptr (cp->net, 0);
-      schedule_assign_vector(ptr, off, sig->value_size(), value, delay);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%assign/v0/x1/d ...\n");
-#endif
-      return true;
-}
-
-/*
- * This is %assign/v0/x1/e <label>, <bit>
- * Index register 0 contains a vector part width.
- * Index register 1 contains the offset into the destination vector.
- */
-bool of_ASSIGN_V0X1E(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = thr->words[0].w_int;
-      long off = thr->words[1].w_int;
-      unsigned bit = cp->bit_idx[0];
-
-      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (cp->net->fil);
-      assert(sig);
-
-	// We fell off the MSB end.
-      if (off >= (long)sig->value_size()) {
-	    thr->event = 0;
-	    thr->ecount = 0;
-	    return true;
-      } else if (off < 0 ) {
-	      // We fell off the LSB end.
-	    if ((unsigned)-off >= wid ) {
-		  thr->event = 0;
-		  thr->ecount = 0;
-		  return true;
-	    }
-	      // Trim the bits before the LSB
-	    wid += off;
-	    bit -= off;
-	    off = 0;
-      }
-
-      assert(wid > 0);
-
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-
-      vvp_net_ptr_t ptr (cp->net, 0);
-	// If the count is zero then just put the value.
-      if (thr->ecount == 0) {
-	    schedule_assign_vector(ptr, off, sig->value_size(), value, 0);
-      } else {
-	    schedule_evctl(ptr, value, off, sig->value_size(), thr->event,
-	                   thr->ecount);
-      }
-
-      thr->event = 0;
-      thr->ecount = 0;
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%assign/v0/x1/e ...\n");
-#endif
-      return true;
-}
-
 /*
  * This is %assign/wr <vpi-label>, <delay>
  *
@@ -1752,18 +1303,6 @@ bool of_ASSIGN_WRE(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-bool of_ASSIGN_X0(vthread_t, vvp_code_t)
-{
-#if 0
-      unsigned char bit_val = thr_get_bit(thr, cp->bit_idx[1]);
-      vvp_ipoint_t itmp = ipoint_index(cp->iptr, thr->words[0].w_int);
-      schedule_assign(itmp, bit_val, cp->bit_idx[0]);
-#else
-      fprintf(stderr, "XXXX forgot how to implement %%assign/x0\n");
-#endif
-      return true;
-}
-
 bool of_BLEND(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t vala = thr->pop_vec4();
@@ -1949,7 +1488,7 @@ bool of_CAST2(vthread_t thr, vvp_code_t)
       return true;
 }
 
-bool of_CMPS(vthread_t thr, vvp_code_t cp)
+bool of_CMPS(vthread_t thr, vvp_code_t)
 {
       vvp_bit4_t eq  = BIT4_1;
       vvp_bit4_t eeq = BIT4_1;
@@ -2039,140 +1578,7 @@ bool of_CMPSTR(vthread_t thr, vvp_code_t)
       return true;
 }
 
-bool of_CMPIS(vthread_t thr, vvp_code_t cp)
-{
-      vvp_bit4_t eq  = BIT4_1;
-      vvp_bit4_t eeq = BIT4_1;
-      vvp_bit4_t lt  = BIT4_0;
-#if 0
-      unsigned idx1 = cp->bit_idx[0];
-      unsigned imm  = cp->bit_idx[1];
-
-      const unsigned end1 = (idx1 < 4)? idx1 : idx1 + cp->number - 1;
-      thr_check_addr(thr, end1);
-      const vvp_bit4_t sig1 = thr_get_bit(thr, end1);
-
-      for (unsigned idx = 0 ;  idx < cp->number ;  idx += 1) {
-	    vvp_bit4_t lv = thr_get_bit(thr, idx1);
-	    vvp_bit4_t rv = (imm & 1)? BIT4_1 : BIT4_0;
-	    imm >>= 1;
-
-	    if (lv > rv) {
-		  lt = BIT4_0;
-		  eeq = BIT4_0;
-	    } else if (lv < rv) {
-		  lt = BIT4_1;
-		  eeq = BIT4_0;
-	    }
-	    if (eq != BIT4_X) {
-		  if ((lv == BIT4_0) && (rv != BIT4_0))
-			eq = BIT4_0;
-		  if ((lv == BIT4_1) && (rv != BIT4_1))
-			eq = BIT4_0;
-		  if (bit4_is_xz(lv) || bit4_is_xz(rv))
-			eq = BIT4_X;
-	    }
-
-	    if (idx1 >= 4) idx1 += 1;
-      }
-
-      if (eq == BIT4_X)
-	    lt = BIT4_X;
-      else if (sig1 == BIT4_1)
-	    lt = BIT4_1;
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%cmpi/s ...\n");
-#endif
-      thr->flags[4] = eq;
-      thr->flags[5] = lt;
-      thr->flags[6] = eeq;
-
-      return true;
-}
-
-/*
- * The of_CMPIU below punts to this function if there are any xz bits
- * in the vector part of the instruction. In this case we know that
- * there is at least 1 xz bit in the left expression (and there are
- * none in the imm value) so the eeq result must be false. Otherwise,
- * the eq result may be 0 or x, and the lt bit is x.
- */
-#if 0
-static bool of_CMPIU_the_hard_way(vthread_t thr, vvp_code_t cp)
-{
-
-      unsigned idx1 = cp->bit_idx[0];
-      unsigned long imm  = cp->bit_idx[1];
-      unsigned wid  = cp->number;
-      if (idx1 >= 4)
-	    thr_check_addr(thr, idx1+wid-1);
-
-      vvp_bit4_t lv = thr_get_bit(thr, idx1);
-      vvp_bit4_t eq  = BIT4_1;
-      for (unsigned idx = 0 ;  idx < wid ;  idx += 1) {
-	    vvp_bit4_t rv = (imm & 1UL)? BIT4_1 : BIT4_0;
-	    imm >>= 1UL;
-
-	    if (bit4_is_xz(lv)) {
-		  eq = BIT4_X;
-	    } else if (lv != rv) {
-		  eq = BIT4_0;
-		  break;
-	    }
-
-	    if (idx1 >= 4) {
-		  idx1 += 1;
-		  if ((idx+1) < wid)
-			lv = thr_get_bit(thr, idx1);
-	    }
-      }
-
-      thr_put_bit(thr, 4, eq);
-      thr_put_bit(thr, 5, BIT4_X);
-      thr_put_bit(thr, 6, BIT4_0);
-
-      return true;
-}
-#endif
-bool of_CMPIU(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned addr = cp->bit_idx[0];
-      unsigned long imm  = cp->bit_idx[1];
-      unsigned wid  = cp->number;
-
-      unsigned long*array = vector_to_array(thr, addr, wid);
-	// If there are xz bits in the right hand expression, then we
-	// have to do the compare the hard way. That is because even
-	// though we know that eeq must be false (the immediate value
-	// cannot have x or z bits) we don't know what the EQ or LT
-	// bits will be.
-      if (array == 0)
-	    return of_CMPIU_the_hard_way(thr, cp);
-
-      unsigned words = (wid+CPU_WORD_BITS-1) / CPU_WORD_BITS;
-      vvp_bit4_t eq  = BIT4_1;
-      vvp_bit4_t lt  = BIT4_0;
-      for (unsigned idx = 0 ; idx < words ; idx += 1, imm = 0UL) {
-	    if (array[idx] == imm)
-		  continue;
-
-	    eq = BIT4_0;
-	    lt = (array[idx] < imm) ? BIT4_1 : BIT4_0;
-      }
-
-      delete[]array;
-
-      thr_put_bit(thr, 4, eq);
-      thr_put_bit(thr, 5, lt);
-      thr_put_bit(thr, 6, eq);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%cmpi/u ...\n");
-#endif
-      return true;
-}
-
-bool of_CMPU_the_hard_way(vthread_t thr, vvp_code_t cp, unsigned wid,
+bool of_CMPU_the_hard_way(vthread_t thr, vvp_code_t, unsigned wid,
 			  const vvp_vector4_t&lval, const vvp_vector4_t&rval)
 {
       vvp_bit4_t eq = BIT4_1;
@@ -2254,7 +1660,7 @@ bool of_CMPU(vthread_t thr, vvp_code_t cp)
 /*
  * %cmp/x
  */
-bool of_CMPX(vthread_t thr, vvp_code_t cp)
+bool of_CMPX(vthread_t thr, vvp_code_t)
 {
       vvp_bit4_t eq = BIT4_1;
       vvp_vector4_t rval = thr->pop_vec4();
@@ -2321,7 +1727,7 @@ bool of_CMPWU(vthread_t thr, vvp_code_t cp)
 /*
  * %cmp/z
  */
-bool of_CMPZ(vthread_t thr, vvp_code_t cp)
+bool of_CMPZ(vthread_t thr, vvp_code_t)
 {
       vvp_bit4_t eq = BIT4_1;
       vvp_vector4_t rval = thr->pop_vec4();
@@ -2410,7 +1816,7 @@ bool of_CVT_RV(vthread_t thr, vvp_code_t)
 /*
  * %cvt/rv/s
  */
-bool of_CVT_RV_S(vthread_t thr, vvp_code_t cp)
+bool of_CVT_RV_S(vthread_t thr, vvp_code_t)
 {
       double val;
       vvp_vector4_t val4 = thr->pop_vec4();
@@ -3319,7 +2725,7 @@ bool of_FREE(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-bool of_INV(vthread_t thr, vvp_code_t cp)
+bool of_INV(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t val = thr->pop_vec4();
       thr->push_vec4(~val);
@@ -3707,86 +3113,6 @@ bool of_LOAD_AR(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-/*
- * %load/av <bit>, <array-label>, <wid> ;
- *
- * <bit> is the thread bit address for the result
- * <array-label> is the array to access, and
- * <wid> is the width of the word to read.
- *
- * The address of the word in the array is in index register 3.
- */
-bool of_LOAD_AV(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned bit = cp->bit_idx[0];
-      unsigned wid = cp->bit_idx[1];
-      unsigned adr = thr->words[3].w_int;
-
-	/* Check the address once, before we scan the vector. */
-      thr_check_addr(thr, bit+wid-1);
-
-	/* The result is 'bx if the address is undefined. */
-      if (thr_get_bit(thr, 4) == BIT4_1) {
-	    vvp_vector4_t tmp (wid, BIT4_X);
-	    thr->bits4.set_vec(bit, tmp);
-	    return true;
-      }
-
-      vvp_vector4_t word = array_get_word(cp->array, adr);
-
-      if (word.size() > wid)
-	    word.resize(wid);
-
-	/* Copy the vector bits into the bits4 vector. Do the copy
-	   directly to skip the excess calls to thr_check_addr. */
-      thr->bits4.set_vec(bit, word);
-
-	/* If the source is shorter than the desired width, then pad
-	   with BIT4_X values. */
-      for (unsigned idx = word.size() ; idx < wid ; idx += 1)
-	    thr->bits4.set_bit(bit+idx, BIT4_X);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%load/av ...\n");
-#endif
-      return true;
-}
-
-#if 0
-/*
- * %load/dar <bit>, <array-label>, <index>;
-*/
-bool of_LOAD_DAR(vthread_t thr, vvp_code_t cp)
-{
-      unsigned bit = cp->bit_idx[0];
-      unsigned wid = cp->bit_idx[1];
-      unsigned adr = thr->words[3].w_int;
-      vvp_net_t*net = cp->net;
-
-      assert(net);
-      vvp_fun_signal_object*obj = dynamic_cast<vvp_fun_signal_object*> (net->fun);
-      assert(obj);
-
-      vvp_darray*darray = obj->get_object().peek<vvp_darray>();
-      assert(darray);
-
-      vvp_vector4_t word;
-      darray->get_word(adr, word);
-
-      if (word.size() != wid) {
-	    cerr << __FILE__ << ":" << __LINE__
-		 << ": %load/dar element word.size()=" << word.size()
-		 << ", expecting wid=" << wid << "." << endl;
-	    abort();
-      }
-
-      thr_check_addr(thr, bit+word.size());
-      thr->bits4.set_vec(bit, word);
-
-      return true;
-}
-#endif
-
 /*
  * %load/dar/r <array-label>;
  */
@@ -3890,111 +3216,6 @@ static void load_vp0_common(vthread_t thr, vvp_code_t cp, const vvp_vector4_t&si
 #endif
 }
 
-/*
- * %load/avp0 <bit>, <array-label>, <wid> ;
- *
- * <bit> is the thread bit address for the result
- * <array-label> is the array to access, and
- * <wid> is the width of the word to read.
- *
- * The address of the word in the array is in index register 3.
- * An integer value from index register 0 is added to the value.
- */
-bool of_LOAD_AVP0(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = cp->bit_idx[1];
-      unsigned adr = thr->words[3].w_int;
-
-	/* The result is 'bx if the address is undefined. */
-      if (thr_get_bit(thr, 4) == BIT4_1) {
-	    unsigned bit = cp->bit_idx[0];
-	    thr_check_addr(thr, bit+wid-1);
-	    vvp_vector4_t tmp (wid, BIT4_X);
-	    thr->bits4.set_vec(bit, tmp);
-	    return true;
-      }
-
-        /* We need a vector this wide to make the math work correctly.
-         * Copy the base bits into the vector, but keep the width. */
-      vvp_vector4_t sig_value(wid, BIT4_0);
-      sig_value.copy_bits(array_get_word(cp->array, adr));
-
-      load_vp0_common(thr, cp, sig_value);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%load/avp0 ...\n");
-#endif
-      return true;
-}
-
-bool of_LOAD_AVP0_S(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned wid = cp->bit_idx[1];
-      unsigned adr = thr->words[3].w_int;
-
-	/* The result is 'bx if the address is undefined. */
-      if (thr_get_bit(thr, 4) == BIT4_1) {
-	    unsigned bit = cp->bit_idx[0];
-	    thr_check_addr(thr, bit+wid-1);
-	    vvp_vector4_t tmp (wid, BIT4_X);
-	    thr->bits4.set_vec(bit, tmp);
-	    return true;
-      }
-
-      vvp_vector4_t tmp (array_get_word(cp->array, adr));
-
-        /* We need a vector this wide to make the math work correctly.
-         * Copy the base bits into the vector, but keep the width. */
-      vvp_vector4_t sig_value(wid, tmp.value(tmp.size()-1));
-      sig_value.copy_bits(tmp);
-
-      load_vp0_common(thr, cp, sig_value);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%load/avp0/s ... \n");
-#endif
-      return true;
-}
-
-/*
- * %load/avx.p <bit>, <array-label>, <wid> ;
- *
- * <bit> is the thread bit address for the result
- * <array-label> is the array to access, and
- * <wid> is the width of the word to read.
- *
- * The address of the word in the array is in index register 3.
- */
-bool of_LOAD_AVX_P(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned bit = cp->bit_idx[0];
-      unsigned index = cp->bit_idx[1];
-      unsigned adr = thr->words[3].w_int;
-
-	/* The result is 'bx if the address is undefined. */
-      if (thr_get_bit(thr, 4) == BIT4_1) {
-	    thr_put_bit(thr, bit, BIT4_X);
-	    return true;
-      }
-
-      long use_index = thr->words[index].w_int;
-
-      vvp_vector4_t word = array_get_word(cp->array, adr);
-
-      if ((use_index >= (long)word.size()) || (use_index < 0)) {
-	    thr_put_bit(thr, bit, BIT4_X);
-      } else {
-	    thr_put_bit(thr, bit, word.value(use_index));
-      }
-
-      thr->words[index].w_int = use_index + 1;
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%load/avx.p ...\n");
-#endif
-      return true;
-}
-
 /*
  * %load/obj <var-label>
  */
@@ -4214,47 +3435,6 @@ bool of_LOAD_VP0_S(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-/*
- * %load/x16 <bit>, <functor>, <wid>
- *
- * <bit> is the destination thread bit and must be >= 4.
- */
-bool of_LOAD_X1P(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-	// <bit> is the thread bit to load
-      assert(cp->bit_idx[0] >= 4);
-      unsigned bit = cp->bit_idx[0];
-      int wid = cp->bit_idx[1];
-
-	// <index> is the canonical base address of the part select.
-      long index = thr->words[1].w_int;
-
-	// <functor> is converted to a vvp_net_t pointer from which we
-	// read our value.
-      vvp_net_t*net = cp->net;
-
-	// For the %load to work, the functor must actually be a
-	// signal functor. Only signals save their vector value.
-      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (net->fil);
-      assert(sig);
-
-      for (long idx = 0 ; idx < wid ; idx += 1) {
-	    long use_index = index + idx;
-	    vvp_bit4_t val;
-	    if (use_index < 0 || use_index >= (signed)sig->value_size())
-		  val = BIT4_X;
-	    else
-		  val = sig->value(use_index);
-
-	    thr_put_bit(thr, bit+idx, val);
-      }
-#else
-      fprintf(stderr, "XXXX NOT IMLEMENTED: %%load/x1p ...\n");
-#endif
-      return true;
-}
-
 static void do_verylong_mod(vthread_t thr,
 			    const vvp_vector4_t&vala, const vvp_vector4_t&valb,
 			    bool left_is_neg, bool right_is_neg)
@@ -4522,57 +3702,6 @@ bool of_MOD_WR(vthread_t thr, vvp_code_t)
       return true;
 }
 
-/*
- * %mov <dest>, <src>, <wid>
- *   This instruction is implemented by the of_MOV function
- *   below. However, during runtime vvp might notice that the
- *   parameters have certain properties that make it possible to
- *   replace the of_MOV opcode with a more specific instruction that
- *   more directly does the job. All the of_MOV*_ functions are
- *   functions that of_MOV might use to replace itself.
- */
-#if 0
-static bool of_MOV1XZ_(vthread_t thr, vvp_code_t cp)
-{
-      thr_check_addr(thr, cp->bit_idx[0]+cp->number-1);
-      vvp_vector4_t tmp (cp->number, thr_index_to_bit4[cp->bit_idx[1]]);
-      thr->bits4.set_vec(cp->bit_idx[0], tmp);
-      return true;
-}
-
-static bool of_MOV_(vthread_t thr, vvp_code_t cp)
-{
-	/* This variant implements the general case that we know
-	   neither the source nor the destination to be <4. Otherwise,
-	   we copy all the bits manually. */
-
-      thr_check_addr(thr, cp->bit_idx[0]+cp->number-1);
-      thr_check_addr(thr, cp->bit_idx[1]+cp->number-1);
-
-      thr->bits4.mov(cp->bit_idx[0], cp->bit_idx[1], cp->number);
-
-      return true;
-}
-#endif
-bool of_MOV(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      assert(cp->bit_idx[0] >= 4);
-
-      if (cp->bit_idx[1] >= 4) {
-	    cp->opcode = &of_MOV_;
-	    return cp->opcode(thr, cp);
-
-      } else {
-	    cp->opcode = &of_MOV1XZ_;
-	    return cp->opcode(thr, cp);
-      }
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%mov ...\n");
-#endif
-      return true;
-}
-
 /*
  * %pad/s <wid>
  */
@@ -4691,38 +3820,10 @@ bool of_MOV_WU(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-bool of_MOVI(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned dst = cp->bit_idx[0];
-      static unsigned long val[8] = {0, 0, 0, 0, 0, 0, 0, 0};
-      unsigned wid = cp->number;
-
-      thr_check_addr(thr, dst+wid-1);
-
-      val[0] = cp->bit_idx[1];
-
-      while (wid > 0) {
-	    unsigned trans = wid;
-	    if (trans > 8*CPU_WORD_BITS)
-		  trans = 8*CPU_WORD_BITS;
-
-	    thr->bits4.setarray(dst, trans, val);
-
-	    val[0] = 0;
-	    wid -= trans;
-	    dst += trans;
-      }
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%movi ...\n");
-#endif
-      return true;
-}
-
 /*
  * %mul
  */
-bool of_MUL(vthread_t thr, vvp_code_t cp)
+bool of_MUL(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t vala = thr->pop_vec4();
       vvp_vector4_t valb = thr->pop_vec4();
@@ -4791,45 +3892,6 @@ bool of_MUL_WR(vthread_t thr, vvp_code_t)
       return true;
 }
 
-bool of_MULI(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned adr = cp->bit_idx[0];
-      unsigned long imm = cp->bit_idx[1];
-      unsigned wid = cp->number;
-
-      assert(adr >= 4);
-
-      unsigned long*val = vector_to_array(thr, adr, wid);
-	// If there are X bits in the value, then return X.
-      if (val == 0) {
-	    vvp_vector4_t tmp(cp->number, BIT4_X);
-	    thr->bits4.set_vec(cp->bit_idx[0], tmp);
-	    return true;
-      }
-
-	// If everything fits in a word, then do it the easy way.
-      if (wid <= CPU_WORD_BITS) {
-	    val[0] *= imm;
-	    thr->bits4.setarray(adr, wid, val);
-	    delete[]val;
-	    return true;
-      }
-
-      unsigned words = (wid+CPU_WORD_BITS-1) / CPU_WORD_BITS;
-      unsigned long*res = new unsigned long[words];
-
-      multiply_array_imm(res, val, words, imm);
-
-      thr->bits4.setarray(adr, wid, res);
-      delete[]val;
-      delete[]res;
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%muli ...\n");
-#endif
-      return true;
-}
-
 bool of_NAND(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t valr = thr->pop_vec4();
@@ -5044,7 +4106,7 @@ bool of_XORR(vthread_t thr, vvp_code_t)
 /*
  * %xnor/r
  */
-bool of_XNORR(vthread_t thr, vvp_code_t cp)
+bool of_XNORR(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t val = thr->pop_vec4();
 
@@ -5077,7 +4139,7 @@ bool of_OR(vthread_t thr, vvp_code_t)
 /*
  * %nor
  */
-bool of_NOR(vthread_t thr, vvp_code_t cp)
+bool of_NOR(vthread_t thr, vvp_code_t)
 {
       vvp_vector4_t valr = thr->pop_vec4();
       vvp_vector4_t vall = thr->pop_vec4();
@@ -5628,29 +4690,6 @@ bool of_SCOPY(vthread_t thr, vvp_code_t)
       return true;
 }
 
-/*
- * This implements the "%set/av <label>, <bit>, <wid>" instruction. In
- * this case, the <label> is an array label, and the <bit> and <wid>
- * are the thread vector of a value to be written in.
- */
-bool of_SET_AV(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      unsigned bit = cp->bit_idx[0];
-      unsigned wid = cp->bit_idx[1];
-      unsigned off = thr->words[1].w_int;
-      unsigned adr = thr->words[3].w_int;
-
-	/* Make a vector of the desired width. */
-      vvp_vector4_t value = vthread_bits_to_vector(thr, bit, wid);
-
-      array_set_word(cp->array, adr, off, value);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%set/av ...\n");
-#endif
-      return true;
-}
-
 /*
  * %set/dar/obj/real <index>
  */
@@ -5766,70 +4805,6 @@ bool of_SET_DAR_OBJ_STR(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-/*
- * Implement the %set/x instruction:
- *
- *      %set/x <functor>, <bit>, <wid>
- *
- * The bit value of a vector go into the addressed functor. Do not
- * transfer bits that are outside the signal range. Get the target
- * vector dimensions from the vvp_fun_signal addressed by the vvp_net
- * pointer.
- */
-bool of_SET_X0(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      vvp_net_t*net = cp->net;
-      unsigned bit = cp->bit_idx[0];
-      unsigned wid = cp->bit_idx[1];
-
-	// Implicitly, we get the base into the target vector from the
-	// X0 register.
-      long index = thr->words[0].w_int;
-
-      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (net->fil);
-      assert(sig);
-
-	// If the entire part is below the beginning of the vector,
-	// then we are done.
-      if (index < 0 && (wid <= (unsigned)-index))
-	    return true;
-
-	// If the entire part is above the end of the vector, then we
-	// are done.
-      if (index >= (long)sig->value_size())
-	    return true;
-
-	// If the part starts below the vector, then skip the first
-	// few bits and reduce enough bits to start at the beginning
-	// of the vector.
-      if (index < 0) {
-	    if (bit >= 4) bit += (unsigned) -index;
-	    wid -= (unsigned) -index;
-	    index = 0;
-      }
-
-	// Reduce the width to keep the part inside the vector.
-      if (index+wid > sig->value_size())
-	    wid = sig->value_size() - index;
-
-      vvp_vector4_t bit_vec(wid);
-      for (unsigned idx = 0 ;  idx < wid ;  idx += 1) {
-	    vvp_bit4_t bit_val = thr_get_bit(thr, bit);
-	    bit_vec.set_bit(idx, bit_val);
-	    if (bit >= 4)
-		  bit += 1;
-      }
-
-      vvp_net_ptr_t ptr (net, 0);
-      vvp_send_vec4_pv(ptr, bit_vec, index, wid, sig->value_size(), thr->wt_context);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%set/x0 ...\n");
-      assert(0);
-#endif
-      return true;
-}
-
 /*
  * %shiftl <idx>
  */
@@ -6430,47 +5405,6 @@ bool of_SUB_WR(vthread_t thr, vvp_code_t)
       return true;
 }
 
-bool of_SUBI(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      assert(cp->bit_idx[0] >= 4);
-
-      unsigned word_count = (cp->number+CPU_WORD_BITS-1)/CPU_WORD_BITS;
-      unsigned long imm = cp->bit_idx[1];
-      unsigned long*lva = vector_to_array(thr, cp->bit_idx[0], cp->number);
-      if (lva == 0)
-	    goto x_out;
-
-
-      unsigned long carry;
-      carry = 1;
-      for (unsigned idx = 0 ;  idx < word_count ;  idx += 1) {
-	    lva[idx] = add_with_carry(lva[idx], ~imm, carry);
-	    imm = 0UL;
-      }
-
-	/* We know from the vector_to_array that the address is valid
-	   in the thr->bitr4 vector, so just do the set bit. */
-
-      thr->bits4.setarray(cp->bit_idx[0], cp->number, lva);
-
-      delete[]lva;
-
-      return true;
-
- x_out:
-      delete[]lva;
-
-      vvp_vector4_t tmp(cp->number, BIT4_X);
-      thr->bits4.set_vec(cp->bit_idx[0], tmp);
-
-      return true;
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%subi ...\n");
-      return true;
-#endif
-}
-
 /*
  * %substr <first>, <last>
  * Pop a string, take the substring (SystemVerilog style), and return
@@ -6524,42 +5458,6 @@ bool of_SUBSTR_VEC4(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-#if 0
-/*
- * %substr/v <bitl>, <index>, <wid>
- */
-bool of_SUBSTR_V(vthread_t thr, vvp_code_t cp)
-{
-	//string&val = thr->peek_str(0);
-      uint32_t bitl = cp->bit_idx[0];
-      uint32_t sel = cp->bit_idx[1];
-      unsigned wid = cp->number;
-
-      thr_check_addr(thr, bitl+wid);
-      assert(bitl >= 4);
-
-      int32_t use_sel = thr->words[sel].w_int;
-
-      vvp_vector4_t tmp (8);
-      unsigned char_count = wid/8;
-      for (unsigned idx = 0 ; idx < char_count ; idx += 1) {
-	    unsigned long byte;
-	    if (use_sel < 0)
-		  byte = 0x00;
-	    else if ((size_t)use_sel >= val.size())
-		  byte = 0x00;
-	    else
-		  byte = val[use_sel];
-
-	    thr->bits4.setarray(bitl, 8, &byte);
-	    bitl += 8;
-	    use_sel += 1;
-      }
-
-      return true;
-}
-#endif
-
 bool of_FILE_LINE(vthread_t, vvp_code_t cp)
 {
       if (show_file_line) {