From 46419663491184df10ea74835a874c7adae63d71 Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Tue, 15 Jul 2003 03:48:07 +0000
Subject: [PATCH]  Obsolete the verilog.1 man page.

---
 verilog.1 | 88 -------------------------------------------------------
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 delete mode 100644 verilog.1

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-.TH verilog 1 "Septemeber 13th, 1999" Version 19990913
-.SH NAME
-verilog - Icarus Verilog Driver
-.SH SYNOPSIS
-.B verilog
-[-Dmacro[=defn]] [-Iincludepath] [-X] [-o outputfilename] [-s topmodule] sourcefile[s]
-.SH DESCRIPTION
-.PP
-\fIverilog\fP is the compiler driver script for compiling Verilog code
-to either a VVM-format (Verilog Virtual Machine) for simulation or to 
-XNF (Xilinx Netlist Format) to be used in Xilinx FPGA's.
-
-\fIverilog\fP is just massaging the input switches and then calls 
-the preprocessor (ivlpp), the compiler (ivl) and (optional) the C++
-compiler.
-
-Please read the official documentation (very minimal at this point)
-on how to use \fIivl et al\fP, since this man page just describes the 
-"easy startscript" \fIverilog\fP.
-
-.SH OPTIONS
-.l
-\fIverilog\fP accepts the following options:
-.TP 8
-.B -D\fImacro\fP
-Defines macro \fImacro\fP with the string  `1' as its definition.
-.TP 8
-.B -D\fImacro=defn\fP
-Defines macro \fImacro\fP as \fIdefn\fP.
-.TP 8
-.B -I\fIincludepath\fP 
-Append path \fIincludepath\fP to list of paths searched for include files.
-.TP 8
-.B -m\fImodule\fP
-Add this module to the list of modules to be loaded by the simulation.
-.B -X
-Generate XNF files as output. Default is VVM-format.
-.TP 8
-.B -x
-Executes the generated file directly after compilation.
-.TP 8
-.B -o \fIfilename\fP
-Place output in the file \fIfilename\fP. If not given, \fIverilog\fP tries to
-make a guess; if the input filename is "hello.v", the output 
-filename will be "hello" (for VVM target) or "hello.xnf" (for XNF target).
-If several files are given on the command line, the \fIlast\fP filename will
-be used.
-.TP 8
-.B -s \fItopmodule name\fP
-To explicitly set the module \fIivl\fP will use as a top-level module.
-
-.SH EXAMPLES 
-These examples assume that you have a Verilog source file called hello.v in
-the current directory
-
-To compile hello.v to an executable file called hello:
-
-	verilog hello.v
-
-To compile hello.v to an executable file called runnable:
-
-	verilog -o runnable hello.v
-
-To compile hello.v to a file in XNF-format called hello.xnf
-
-	verilog -X hello.v
-
-
-.SH "ENVIRONMENT"
-.ta \w'VPI_MODULE_PATH   'u
-VPI_MODULE_PATH	path to PLI modules
-
-.SH "AUTHORS"
-.nf
-.ta \w'verilog  'u
-verilog	Stefan Petersen (spe@geda.seul.org)
-ivlpp	Steve Williams (steve@icarus.com)
-ivl	Steve Williams (steve@icarus.com)
-
-.SH SEE ALSO
-.BR ivlpp (N/A)
-.BR ivl (N/A)
-.SH COPYRIGHT
-.nf
-Copyright \(co  1999 Stefan Petersen
-
-This document can be freely redistributed according to the terms of the 
-GNU General Public License version 2.0