From 3ec8a867db4319b197c30a6f32d18e470e69aac2 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Tue, 24 Jun 2008 08:46:16 -0700 Subject: [PATCH] Spelling fixes comments, documentation, a variable name, and a couple of messages --- elaborate.cc | 4 ++-- scripts/CREATE_VERSION.sh | 2 +- t-dll.cc | 2 +- tgt-fpga/iverilog-fpga.man | 2 +- vvp/README.txt | 2 +- vvp/npmos.h | 2 +- vvp/opcodes.txt | 2 +- vvp/schedule.cc | 2 +- vvp/vvp_island.cc | 6 +++--- 9 files changed, 12 insertions(+), 12 deletions(-) diff --git a/elaborate.cc b/elaborate.cc index a0d8d73a0..4c7df215b 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -1158,7 +1158,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const /* Input to module. elaborate the expression to the desired width. If this in an instance - array, then let the net determine it's own + array, then let the net determine its own width. We use that, then, to decide how to hook it up. @@ -2954,7 +2954,7 @@ NetForce* PForce::elaborate(Design*des, NetScope*scope) const dev = new NetForce(lval, rexp); if (debug_elaborate) { - cerr << get_fileline() << ": debug: ELaborate force," + cerr << get_fileline() << ": debug: Elaborate force," << " lval width=" << lval->lwidth() << " rval width=" << rexp->expr_width() << " rval=" << *rexp diff --git a/scripts/CREATE_VERSION.sh b/scripts/CREATE_VERSION.sh index 2cbec4707..ac018e4a0 100644 --- a/scripts/CREATE_VERSION.sh +++ b/scripts/CREATE_VERSION.sh @@ -8,6 +8,6 @@ # sh scripts/CREATE_VERSION.sh # -echo "Building verion.h with git describe" +echo "Building version.h with git describe" tmp=`git describe | sed -e 's;\(.*\);#define VERSION_TAG "\1";'` echo "$tmp" > version.h diff --git a/t-dll.cc b/t-dll.cc index 5b6a22a52..0d9380ac4 100644 --- a/t-dll.cc +++ b/t-dll.cc @@ -1946,7 +1946,7 @@ void dll_target::lpm_mux(const NetMux*net) { ivl_lpm_t obj = new struct ivl_lpm_s; obj->type = IVL_LPM_MUX; - obj->name = net->name(); // The NetMux perallocates its name. + obj->name = net->name(); // The NetMux permallocates its name. obj->scope = find_scope(des_, net->scope()); assert(obj->scope); diff --git a/tgt-fpga/iverilog-fpga.man b/tgt-fpga/iverilog-fpga.man index 608077d81..a9f263a9c 100644 --- a/tgt-fpga/iverilog-fpga.man +++ b/tgt-fpga/iverilog-fpga.man @@ -160,7 +160,7 @@ device pins are connected. .SH EXAMPLES .TB 8 -.I COMPILING WITH XILINX FOUNDATION/iSE +.I COMPILING WITH XILINX FOUNDATION/ISE Compile a single-file design with command line tools like so: .nf diff --git a/vvp/README.txt b/vvp/README.txt index cdd51086f..188f58e36 100644 --- a/vvp/README.txt +++ b/vvp/README.txt @@ -802,7 +802,7 @@ syntax is: The is the label for a variable array, and the is the canonical word index as an unsigned integer. The second form -retrives the index from thread space ( bits starting at ). +retrieves the index from thread space ( bits starting at ). * The &PV<> argument diff --git a/vvp/npmos.h b/vvp/npmos.h index 0f938b382..dc97b7290 100644 --- a/vvp/npmos.h +++ b/vvp/npmos.h @@ -43,7 +43,7 @@ * * This class also implements the NMOS device, which is the same as * the PMOS device, but the Control input inverted. The enable_invert - * flag to the costructor activates this invertion. + * flag to the constructor activates this inversion. */ class vvp_fun_pmos_ : public vvp_net_fun_t { diff --git a/vvp/opcodes.txt b/vvp/opcodes.txt index 292d7fb53..ef5c909b1 100644 --- a/vvp/opcodes.txt +++ b/vvp/opcodes.txt @@ -474,7 +474,7 @@ part. If any bit of the desired value is outside the vector, then that bit is set to X. The index register 1 is interpreted as a signed value. Even though the -address is cannonical (from 0 to the width of the signal) the value in +address is canonical (from 0 to the width of the signal) the value in index register 1 may be <0 or >=wid. The load instruction handles filling in the out-of-bounds bits with x. diff --git a/vvp/schedule.cc b/vvp/schedule.cc index c2546120d..50944c695 100644 --- a/vvp/schedule.cc +++ b/vvp/schedule.cc @@ -780,7 +780,7 @@ void schedule_simulate(void) ctim->rwsync = 0; /* If out of rw events, then run the rosync - events and delete this timestep. This also + events and delete this time step. This also deletes threads as needed. */ if (ctim->active == 0) { run_rosync(ctim); diff --git a/vvp/vvp_island.cc b/vvp/vvp_island.cc index 439afca78..c258309a6 100644 --- a/vvp/vvp_island.cc +++ b/vvp/vvp_island.cc @@ -357,11 +357,11 @@ class vvp_island_tran : public vvp_island { void vvp_island_tran::run_island() { // Test to see if any of the branches are enabled. - bool runable = false; + bool runnable = false; for (vvp_island_branch*cur = branches_ ; cur ; cur = cur->next_branch) { - runable |= cur->run_test_enabled(); + runnable |= cur->run_test_enabled(); } - if (runable == false) + if (runnable == false) return; for (vvp_island_branch*cur = branches_ ; cur ; cur = cur->next_branch)