From de9e3b791bfa94cabe6b6ac7f1134ba8131decf5 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 12 Mar 2022 22:40:14 +0100 Subject: [PATCH 1/3] Correctly handle separate port type declaration for atom2 types When using non-ANSI style port declarations it is possible to declare the port direction and the data type for the port in separate statements. E.g. ``` input x; reg x; ``` When using packed array dimensions they must match for both declarations. E.g. ``` input [3:0] x; reg [3:0] x; ``` But this only applies to vector types, i.e. the packed dimension is explicitly declared. It does not apply to the atom2 types which have an implicit packed dimension. The current implementation requires that even for atom2 types the implicit dimension needs to be explicitly declared in the port direction. E.g. the following will result in a elaboration error complaining about a packed dimension mismatch. ``` module test; output x; byte x; endmodule ``` Currently atom2_type_t's are deconstructed into base type, range and signdness in the parser. That data is then passed to the signal elaboration, which will then construct a netvector_t from it. This makes it impossible to e.g. differentiate between `bit signed [31:0]` and `int` during elaboration. Instead of breaking the data type apart pass it as the data_type_t of the signal and use the elaborate_type() method in the signal elaboration to generate the netvector_t. Signed-off-by: Lars-Peter Clausen --- elab_sig.cc | 3 ++- pform.cc | 43 +++---------------------------------------- 2 files changed, 5 insertions(+), 41 deletions(-) diff --git a/elab_sig.cc b/elab_sig.cc index f472c7595..646da858d 100644 --- a/elab_sig.cc +++ b/elab_sig.cc @@ -941,7 +941,8 @@ ivl_type_t PWire::elaborate_type(Design*des, NetScope*scope, dynamic_cast(set_data_type_) || dynamic_cast(set_data_type_) || dynamic_cast(set_data_type_) || - dynamic_cast(set_data_type_)) { + dynamic_cast(set_data_type_) || + dynamic_cast(set_data_type_)) { ivl_type_t use_type = set_data_type_->elaborate_type(des, scope); ivl_assert(*this, packed_dimensions.empty()); return use_type; diff --git a/pform.cc b/pform.cc index 9fcaeabae..fcd639a93 100644 --- a/pform.cc +++ b/pform.cc @@ -2601,11 +2601,6 @@ void pform_module_define_port(const struct vlltype&li, data_type = vec_type->base_type; signed_flag = vec_type->signed_flag; prange = vec_type->pdims.get(); - } else if (atom2_type_t*atype = dynamic_cast(vtype)) { - data_type = IVL_VT_BOOL; - signed_flag = atype->signed_flag; - prange = make_range_from_width(atype->type_code); - } else if (real_type_t*rtype = dynamic_cast(vtype)) { data_type = IVL_VT_REAL; signed_flag = true; @@ -2959,11 +2954,8 @@ vector*pform_make_task_ports(const struct vlltype&loc, vtype = uarray->base_type; } - if (atom2_type_t*atype = dynamic_cast (vtype)) { - list*range_tmp = make_range_from_width(atype->type_code); - ret = pform_make_task_ports(loc, pt, IVL_VT_BOOL, - atype->signed_flag, - range_tmp, ports); + if (dynamic_cast (vtype)) { + ret = do_make_task_ports(loc, pt, IVL_VT_BOOL, vtype, ports); } if (vector_type_t*vec_type = dynamic_cast (vtype)) { @@ -3431,30 +3423,6 @@ void pform_set_port_type(const struct vlltype&li, delete attr; } -static void pform_set_integer_2atom(uint64_t width, bool signed_flag, perm_string name) -{ - PWire*cur = pform_get_wire_in_scope(name); - assert(cur); - - cur->set_signed(signed_flag); - - pform_range_t rng; - rng.first = new PENumber(new verinum(width-1, integer_width)); - rng.second = new PENumber(new verinum((uint64_t)0, integer_width)); - listrlist; - rlist.push_back(rng); - cur->set_range(rlist, SR_NET); -} - -static void pform_set_integer_2atom(uint64_t width, bool signed_flag, list*names) -{ - for (list::iterator cur = names->begin() - ; cur != names->end() ; ++ cur ) { - perm_string txt = *cur; - pform_set_integer_2atom(width, signed_flag, txt); - } -} - /* * This function detects the derived class for the given type and * dispatches the type to the proper subtype function. @@ -3471,12 +3439,7 @@ void pform_set_data_type(const struct vlltype&li, data_type_t*data_type, listbase_type; - if (atom2_type_t*atom2_type = dynamic_cast (data_type)) { - pform_set_integer_2atom(atom2_type->type_code, atom2_type->signed_flag, names); - vt = IVL_VT_BOOL; - } - - else if (vector_type_t*vec_type = dynamic_cast (data_type)) { + if (vector_type_t*vec_type = dynamic_cast (data_type)) { if (net_type==NetNet::REG && vec_type->integer_flag) net_type=NetNet::INTEGER; From f6042033d076e70171cdbcfa14bb98da7027f666 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 12 Mar 2022 21:10:19 +0100 Subject: [PATCH 2/3] Correctly handle separate port type declaration for `integer` and `time` When using non-ANSI style port declarations it is possible to declare the port direction and the data type for the port in separate statements. E.g. ``` input x; reg x; ``` When using packed array dimensions they must match for both declarations. E.g. ``` input [3:0] x; reg [3:0] x; ``` But this only applies for vector types, i.e. the packed dimension is explicitly declared. It does not apply to the `integer` and `time` types, which have an implicit packed dimension. The current implementation requires that even for `integer` and `time` types the implicit dimension needs to be explicitly declared in the port direction. E.g. the following will result in a elaboration error complaining about a packed dimension mismatch. ``` module test; output x; integer x; endmodule ``` Currently the parser creates a vector_type_t for `time` and `integer`. This means that e.g. `time` and `reg [63:0]` are indistinguishable during elaboration, even though they require different behavior. To fix let the atom2_type_t handle `integer` and `time`. Since it no longer exclusively handles 2-state types, rename it to atom_type_t. This also fixes a problem with the vlog95 target unit tests. The vlog95 target translates ``` module test(output integer x); endmodule ``` to ``` module test(x); output x; integer x; endmodule ``` which then fails when being elaborated again. There were some regression tests that were failing because of this that will now pass. Signed-off-by: Lars-Peter Clausen --- PWire.cc | 34 +--------------------------------- PWire.h | 2 -- elab_sig.cc | 3 +-- elab_type.cc | 21 +++++++++++++++------ link_const.cc | 2 +- netlist.cc | 3 --- netlist.h | 2 +- netvector.cc | 19 +++++++++++-------- netvector.h | 4 +++- parse.y | 45 ++++++++++++++++++--------------------------- pform.cc | 17 +++++------------ pform_dump.cc | 34 +++++++++++++++++++++++++++------- pform_types.cc | 12 +++++++++--- pform_types.h | 20 +++++++++++++++----- 14 files changed, 107 insertions(+), 111 deletions(-) diff --git a/PWire.cc b/PWire.cc index 5cba7ef97..3591657b3 100644 --- a/PWire.cc +++ b/PWire.cc @@ -29,16 +29,11 @@ PWire::PWire(perm_string n, NetNet::PortType pt, ivl_variable_type_t dt) : name_(n), type_(t), port_type_(pt), data_type_(dt), - signed_(false), isint_(false), + signed_(false), port_set_(false), net_set_(false), is_scalar_(false), error_cnt_(0), uarray_type_(0), set_data_type_(0), discipline_(0) { - if (t == NetNet::INTEGER) { - type_ = NetNet::REG; - signed_ = true; - isint_ = true; - } } NetNet::Type PWire::get_wire_type() const @@ -64,18 +59,9 @@ bool PWire::set_wire_type(NetNet::Type t) type_ = t; return true; } - if (t == NetNet::INTEGER) { - type_ = NetNet::REG; - isint_ = true; - return true; - } if (t == NetNet::IMPLICIT_REG) return true; return false; case NetNet::REG: - if (t == NetNet::INTEGER) { - isint_ = true; - return true; - } if (t == NetNet::REG) return true; return false; default: @@ -146,18 +132,6 @@ bool PWire::get_signed() const return signed_; } -bool PWire::get_isint() const -{ - if (isint_) - return true; - - if (vector_type_t*tmp = dynamic_cast(set_data_type_)) { - return tmp->integer_flag; - } - - return false; -} - void PWire::set_range_scalar(PWSRType type) { is_scalar_ = true; @@ -267,11 +241,6 @@ void PWire::set_data_type(data_type_t*type) { assert(set_data_type_ == 0 || set_data_type_ == type); set_data_type_ = type; - - if (vector_type_t*tmp = dynamic_cast(type)) { - if (tmp->integer_flag) - isint_ = true; - } } void PWire::set_discipline(ivl_discipline_t d) @@ -289,7 +258,6 @@ PNamedItem::SymbolType PWire::symbol_type() const { switch (type_) { case NetNet::IMPLICIT_REG: - case NetNet::INTEGER: case NetNet::REG: return VAR; default: diff --git a/PWire.h b/PWire.h index dbf27dffd..dfc70970d 100644 --- a/PWire.h +++ b/PWire.h @@ -70,7 +70,6 @@ class PWire : public PNamedItem { void set_signed(bool flag); bool get_signed() const; - bool get_isint() const; bool set_data_type(ivl_variable_type_t dt); ivl_variable_type_t get_data_type() const; @@ -101,7 +100,6 @@ class PWire : public PNamedItem { NetNet::PortType port_type_; ivl_variable_type_t data_type_; bool signed_; - bool isint_; // original type of integer // These members hold expressions for the bit width of the // wire. If they do not exist, the wire is 1 bit wide. If they diff --git a/elab_sig.cc b/elab_sig.cc index 646da858d..7cb636ac3 100644 --- a/elab_sig.cc +++ b/elab_sig.cc @@ -942,7 +942,7 @@ ivl_type_t PWire::elaborate_type(Design*des, NetScope*scope, dynamic_cast(set_data_type_) || dynamic_cast(set_data_type_) || dynamic_cast(set_data_type_) || - dynamic_cast(set_data_type_)) { + dynamic_cast(set_data_type_)) { ivl_type_t use_type = set_data_type_->elaborate_type(des, scope); ivl_assert(*this, packed_dimensions.empty()); return use_type; @@ -967,7 +967,6 @@ ivl_type_t PWire::elaborate_type(Design*des, NetScope*scope, netvector_t*vec = new netvector_t(packed_dimensions, use_data_type); vec->set_signed(get_signed()); - vec->set_isint(get_isint()); return vec; } diff --git a/elab_type.cc b/elab_type.cc index ecd81e098..b77138ac3 100644 --- a/elab_type.cc +++ b/elab_type.cc @@ -66,28 +66,37 @@ ivl_type_t data_type_t::elaborate_type_raw(Design*des, NetScope*) const return 0; } -ivl_type_t atom2_type_t::elaborate_type_raw(Design*des, NetScope*) const +ivl_type_t atom_type_t::elaborate_type_raw(Design*des, NetScope*) const { switch (type_code) { - case 64: + case INTEGER: + return netvector_t::integer_type(signed_flag); + + case TIME: + if (signed_flag) + return &netvector_t::time_signed; + else + return &netvector_t::time_unsigned; + + case LONGINT: if (signed_flag) return &netvector_t::atom2s64; else return &netvector_t::atom2u64; - case 32: + case INT: if (signed_flag) return &netvector_t::atom2s32; else return &netvector_t::atom2u32; - case 16: + case SHORTINT: if (signed_flag) return &netvector_t::atom2s16; else return &netvector_t::atom2u16; - case 8: + case BYTE: if (signed_flag) return &netvector_t::atom2s8; else @@ -95,7 +104,7 @@ ivl_type_t atom2_type_t::elaborate_type_raw(Design*des, NetScope*) const default: cerr << get_fileline() << ": internal error: " - << "atom2_type_t type_code=" << type_code << "." << endl; + << "atom_type_t type_code=" << type_code << "." << endl; des->errors += 1; return 0; } diff --git a/link_const.cc b/link_const.cc index 447c789c8..5887a4aa9 100644 --- a/link_const.cc +++ b/link_const.cc @@ -293,7 +293,7 @@ vector Nexus::driven_mask(void) const // information from this node, move on. if (const NetNet*sig = dynamic_cast (obj)) { NetNet::Type sig_type = sig->type(); - if (sig_type==NetNet::INTEGER || sig_type==NetNet::REG) { + if (sig_type==NetNet::REG) { for (size_t idx = 0 ; idx < mask.size() ; idx += 1) mask[idx] = true; return mask; diff --git a/netlist.cc b/netlist.cc index 7b23b782b..a4b05c413 100644 --- a/netlist.cc +++ b/netlist.cc @@ -51,9 +51,6 @@ ostream& operator<< (ostream&o, NetNet::Type t) case NetNet::IMPLICIT_REG: o << "reg /*implicit*/"; break; - case NetNet::INTEGER: - o << "integer"; - break; case NetNet::REG: o << "reg"; break; diff --git a/netlist.h b/netlist.h index ff7cf133d..093a05338 100644 --- a/netlist.h +++ b/netlist.h @@ -664,7 +664,7 @@ struct PortInfo class NetNet : public NetObj, public PortType { public: - enum Type ENUM_UNSIGNED_INT { NONE, IMPLICIT, IMPLICIT_REG, INTEGER, WIRE, TRI, TRI1, + enum Type ENUM_UNSIGNED_INT { NONE, IMPLICIT, IMPLICIT_REG, WIRE, TRI, TRI1, SUPPLY0, SUPPLY1, WAND, TRIAND, TRI0, WOR, TRIOR, REG, UNRESOLVED_WIRE }; diff --git a/netvector.cc b/netvector.cc index 4d235eb22..86f3d1637 100644 --- a/netvector.cc +++ b/netvector.cc @@ -32,15 +32,18 @@ netvector_t netvector_t::atom2u16 (IVL_VT_BOOL, 15, 0, false); netvector_t netvector_t::atom2s8 (IVL_VT_BOOL, 7, 0, true); netvector_t netvector_t::atom2u8 (IVL_VT_BOOL, 7, 0, false); -static netvector_t* save_integer_type = 0; -const netvector_t* netvector_t::integer_type() -{ - if (save_integer_type) - return save_integer_type; +netvector_t netvector_t::time_signed (IVL_VT_LOGIC, 63, 0, true); +netvector_t netvector_t::time_unsigned (IVL_VT_LOGIC, 63, 0, false); - save_integer_type = new netvector_t(IVL_VT_LOGIC, integer_width-1, 0, true); - save_integer_type->set_isint(true); - return save_integer_type; +static netvector_t* save_integer_type[2]; +const netvector_t* netvector_t::integer_type(bool is_signed) +{ + if (save_integer_type[is_signed]) + return save_integer_type[is_signed]; + + save_integer_type[is_signed] = new netvector_t(IVL_VT_LOGIC, integer_width-1, 0, is_signed); + save_integer_type[is_signed]->set_isint(true); + return save_integer_type[is_signed]; } //netvector_t netvector_t::scalar_bool (IVL_VT_BOOL); diff --git a/netvector.h b/netvector.h index 2775a718d..c79672900 100644 --- a/netvector.h +++ b/netvector.h @@ -75,9 +75,11 @@ class netvector_t : public ivl_type_s { static netvector_t atom2u16; static netvector_t atom2s8; static netvector_t atom2u8; + static netvector_t time_signed; + static netvector_t time_unsigned; static netvector_t scalar_bool; static netvector_t scalar_logic; - static const netvector_t*integer_type(); + static const netvector_t*integer_type(bool is_signed = true); private: bool test_compatibility(ivl_type_t that) const; diff --git a/parse.y b/parse.y index 1e802d8a4..a7190d63a 100644 --- a/parse.y +++ b/parse.y @@ -380,6 +380,8 @@ static void current_function_set_statement(const YYLTYPE&loc, std::vector non_integer_type %type assert_or_assume %type deferred_mode -%type atom2_type +%type atom_type %type module_start module_end %type lifetime lifetime_opt @@ -1224,20 +1226,14 @@ simple_packed_type /* Integer and vector types */ FILE_NAME(tmp, @1); $$ = tmp; } - | atom2_type signed_unsigned_opt - { atom2_type_t*tmp = new atom2_type_t($1, $2); + | atom_type signed_unsigned_opt + { atom_type_t*tmp = new atom_type_t($1, $2); FILE_NAME(tmp, @1); $$ = tmp; } - | K_integer signed_unsigned_opt - { std::list*pd = make_range_from_width(integer_width); - vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $2, pd); - tmp->integer_flag = true; - $$ = tmp; - } | K_time unsigned_signed_opt - { std::list*pd = make_range_from_width(64); - vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $2, pd); + { atom_type_t*tmp = new atom_type_t(atom_type_t::TIME, $2); + FILE_NAME(tmp, @1); $$ = tmp; } ; @@ -2184,20 +2180,14 @@ simple_type_or_string /* IEEE1800-2005: A.2.2.1 */ FILE_NAME(tmp, @1); $$ = tmp; } - | atom2_type - { atom2_type_t*tmp = new atom2_type_t($1, true); + | atom_type + { atom_type_t*tmp = new atom_type_t($1, true); FILE_NAME(tmp, @1); $$ = tmp; } - | K_integer - { std::list*pd = make_range_from_width(integer_width); - vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, true, pd); - tmp->integer_flag = true; - $$ = tmp; - } | K_time - { std::list*pd = make_range_from_width(64); - vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, pd); + { atom_type_t*tmp = new atom_type_t(atom_type_t::TIME, false); + FILE_NAME(tmp, @1); $$ = tmp; } | K_string @@ -2750,7 +2740,7 @@ enum_base_type /* IEEE 1800-2012 A.2.2.1 */ } } | - { $$ = new atom2_type_t(32, true); + { $$ = new atom_type_t(atom_type_t::INT, true); FILE_NAME($$, @0); } ; @@ -4604,11 +4594,12 @@ signed_unsigned_opt * In some places we can take any of the 4 2-value atom-type * names. All the context needs to know if that type is its width. */ -atom2_type - : K_byte { $$ = 8; } - | K_shortint { $$ = 16; } - | K_int { $$ = 32; } - | K_longint { $$ = 64; } +atom_type + : K_byte { $$ = atom_type_t::BYTE; } + | K_shortint { $$ = atom_type_t::SHORTINT; } + | K_int { $$ = atom_type_t::INT; } + | K_longint { $$ = atom_type_t::LONGINT; } + | K_integer { $$ = atom_type_t::INTEGER; } ; /* An lpvalue is the expression that can go on the left side of a diff --git a/pform.cc b/pform.cc index fcd639a93..0fd56df41 100644 --- a/pform.cc +++ b/pform.cc @@ -2862,8 +2862,7 @@ static vector*pform_make_task_ports(const struct vlltype&loc, ivl_variable_type_t vtype, bool signed_flag, list*range, - list*ports, - bool isint = false) + list*ports) { assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT); assert(ports); @@ -2884,10 +2883,6 @@ static vector*pform_make_task_ports(const struct vlltype&loc, } curw->set_signed(signed_flag); - if (isint) { - bool flag = curw->set_wire_type(NetNet::INTEGER); - assert(flag); - } /* If there is a range involved, it needs to be set. */ if (range) { @@ -2954,8 +2949,9 @@ vector*pform_make_task_ports(const struct vlltype&loc, vtype = uarray->base_type; } - if (dynamic_cast (vtype)) { - ret = do_make_task_ports(loc, pt, IVL_VT_BOOL, vtype, ports); + if (dynamic_cast (vtype)) { + ret = do_make_task_ports(loc, pt, vtype->figure_packed_base_type(), + vtype, ports); } if (vector_type_t*vec_type = dynamic_cast (vtype)) { @@ -2966,7 +2962,7 @@ vector*pform_make_task_ports(const struct vlltype&loc, ret = pform_make_task_ports(loc, pt, base_type, vec_type->signed_flag, copy_range(vec_type->pdims.get()), - ports, vec_type->integer_flag); + ports); } if (/*real_type_t*real_type = */ dynamic_cast (vtype)) { @@ -3440,9 +3436,6 @@ void pform_set_data_type(const struct vlltype&li, data_type_t*data_type, listbase_type; if (vector_type_t*vec_type = dynamic_cast (data_type)) { - if (net_type==NetNet::REG && vec_type->integer_flag) - net_type=NetNet::INTEGER; - pform_set_net_range(names, vec_type->pdims.get(), vec_type->signed_flag, 0); vt = vec_type->base_type; diff --git a/pform_dump.cc b/pform_dump.cc index 0c0874d00..38c1675cc 100644 --- a/pform_dump.cc +++ b/pform_dump.cc @@ -173,13 +173,36 @@ ostream& data_type_t::debug_dump(ostream&out) const return out; } -ostream& atom2_type_t::debug_dump(ostream&out) const +ostream& atom_type_t::debug_dump(ostream&out) const { if (signed_flag) - out << "signed-"; + out << "signed "; else - out << "unsigned-"; - out << "int(" << type_code << ")"; + out << "unsigned "; + + switch (type_code) { + case INTEGER: + out << "integer"; + break; + case TIME: + out << "time"; + break; + case LONGINT: + out << "longint"; + break; + case INT: + out << "int"; + break; + case SHORTINT: + out << "shortint"; + break; + case BYTE: + out << "byte"; + break; + default: + assert(0); + break; + } return out; } @@ -584,9 +607,6 @@ void PWire::dump(ostream&out, unsigned ind) const if (signed_) { out << " signed"; } - if (get_isint()) { - out << " integer"; - } if (is_scalar_) { out << " scalar"; } diff --git a/pform_types.cc b/pform_types.cc index 28dfe15fc..7df2ccbc2 100644 --- a/pform_types.cc +++ b/pform_types.cc @@ -53,12 +53,18 @@ ivl_variable_type_t enum_type_t::figure_packed_base_type() const return base_type->figure_packed_base_type(); } -ivl_variable_type_t atom2_type_t::figure_packed_base_type() const +ivl_variable_type_t atom_type_t::figure_packed_base_type() const { - return IVL_VT_BOOL; + switch (type_code) { + case TIME: + case INT: + return IVL_VT_LOGIC; + default: + return IVL_VT_BOOL; + } } -atom2_type_t size_type (32, true); +atom_type_t size_type (atom_type_t::INT, true); PNamedItem::SymbolType enum_type_t::symbol_type() const { diff --git a/pform_types.h b/pform_types.h index b32f674bd..dc4bb8da4 100644 --- a/pform_types.h +++ b/pform_types.h @@ -208,10 +208,20 @@ struct struct_type_t : public data_type_t { std::unique_ptr< std::list > members; }; -struct atom2_type_t : public data_type_t { - inline explicit atom2_type_t(int tc, bool flag) - : type_code(tc), signed_flag(flag) { } - int type_code; +struct atom_type_t : public data_type_t { + enum type_code { + INTEGER, + TIME, + BYTE, + SHORTINT, + INT, + LONGINT + }; + + explicit atom_type_t(enum type_code tc, bool flag) : type_code(tc), + signed_flag(flag) { } + + enum type_code type_code; bool signed_flag; virtual std::ostream& debug_dump(std::ostream&out) const; @@ -221,7 +231,7 @@ struct atom2_type_t : public data_type_t { ivl_variable_type_t figure_packed_base_type() const; }; -extern atom2_type_t size_type; +extern atom_type_t size_type; /* * The vector_type_t class represents types in the old Verilog From 4c9af1c47a55feff1c3f012eda28e2f23ab33148 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 16 Mar 2022 09:10:52 +0100 Subject: [PATCH 3/3] Add regression tests for non-ANSI integer module ports Check that it is possible to declare the type separately from the direction for non-ANSI integer, time and atom2 ports. Check that it is possible to both declare the type before and after the direction. For integer, time and atom2 types the range specification on the port direction declaration should be empty, rather than the implicit packed dimension of the integer type. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_nonansi_int1.v | 24 +++++++++++++++++++++++ ivtest/ivltests/module_nonansi_int2.v | 23 ++++++++++++++++++++++ ivtest/ivltests/module_nonansi_integer1.v | 17 ++++++++++++++++ ivtest/ivltests/module_nonansi_integer2.v | 16 +++++++++++++++ ivtest/ivltests/module_nonansi_time1.v | 17 ++++++++++++++++ ivtest/ivltests/module_nonansi_time2.v | 16 +++++++++++++++ ivtest/regress-sv.list | 2 ++ ivtest/regress-vlg.list | 4 ++++ ivtest/regress-vlog95.list | 2 ++ 9 files changed, 121 insertions(+) create mode 100644 ivtest/ivltests/module_nonansi_int1.v create mode 100644 ivtest/ivltests/module_nonansi_int2.v create mode 100644 ivtest/ivltests/module_nonansi_integer1.v create mode 100644 ivtest/ivltests/module_nonansi_integer2.v create mode 100644 ivtest/ivltests/module_nonansi_time1.v create mode 100644 ivtest/ivltests/module_nonansi_time2.v diff --git a/ivtest/ivltests/module_nonansi_int1.v b/ivtest/ivltests/module_nonansi_int1.v new file mode 100644 index 000000000..e501eff72 --- /dev/null +++ b/ivtest/ivltests/module_nonansi_int1.v @@ -0,0 +1,24 @@ +// Check that it is possible to declare the data type for an atom2 type module +// port separately from the direction for non-ANSI style port declarations. +// declarations. + +module test(x, y, z, w); + output x; + output y; + output z; + output w; + byte x; + shortint y; + int z; + longint w; + + initial begin + if ($bits(x) == 8 && $bits(y) == 16 && + $bits(z) == 32 && $bits(w) == 64) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/ivltests/module_nonansi_int2.v b/ivtest/ivltests/module_nonansi_int2.v new file mode 100644 index 000000000..fdabc8a08 --- /dev/null +++ b/ivtest/ivltests/module_nonansi_int2.v @@ -0,0 +1,23 @@ +// Check that it is possible to declare the data type for an atom2 type module +// port before the direction for non-ANSI style port declarations. + +module test(x, y, z, w); + byte x; + shortint y; + int z; + longint w; + output x; + output y; + output z; + output w; + + initial begin + if ($bits(x) == 8 && $bits(y) == 16 && + $bits(z) == 32 && $bits(w) == 64) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/ivltests/module_nonansi_integer1.v b/ivtest/ivltests/module_nonansi_integer1.v new file mode 100644 index 000000000..4ba0516ba --- /dev/null +++ b/ivtest/ivltests/module_nonansi_integer1.v @@ -0,0 +1,17 @@ +// Check that it is possible to declare the data type for an integer type module +// port separately from the direction for non-ANSI style port declarations. +// declarations. + +module test(x); + output x; + integer x; + + initial begin + if ($bits(x) == $bits(integer)) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/ivltests/module_nonansi_integer2.v b/ivtest/ivltests/module_nonansi_integer2.v new file mode 100644 index 000000000..5326e3020 --- /dev/null +++ b/ivtest/ivltests/module_nonansi_integer2.v @@ -0,0 +1,16 @@ +// Check that it is possible to declare the data type for an integer type module +// port before the direction for non-ANSI style port declarations. + +module test(x); + integer x; + output x; + + initial begin + if ($bits(x) == $bits(integer)) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/ivltests/module_nonansi_time1.v b/ivtest/ivltests/module_nonansi_time1.v new file mode 100644 index 000000000..628e73353 --- /dev/null +++ b/ivtest/ivltests/module_nonansi_time1.v @@ -0,0 +1,17 @@ +// Check that it is possible to declare the data type for a time type module +// port separately from the direction for non-ANSI style port declarations. +// declarations. + +module test(x); + output x; + time x; + + initial begin + if ($bits(x) == 64) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/ivltests/module_nonansi_time2.v b/ivtest/ivltests/module_nonansi_time2.v new file mode 100644 index 000000000..c897319f8 --- /dev/null +++ b/ivtest/ivltests/module_nonansi_time2.v @@ -0,0 +1,16 @@ +// Check that it is possible to declare the data type for a time type module +// port before the direction for non-ANSI style port declarations. + +module test(x); + time x; + output x; + + initial begin + if ($bits(x) == 64) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end + +endmodule diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list index 8312bd6b3..25d7a3cef 100644 --- a/ivtest/regress-sv.list +++ b/ivtest/regress-sv.list @@ -338,6 +338,8 @@ logp2 normal,-g2005-sv ivltests mod_inst_pkg normal,-g2009 ivltests module_nonansi_enum1 normal,-g2005-sv ivltests module_nonansi_enum2 normal,-g2005-sv ivltests +module_nonansi_int1 normal,-g2005-sv ivltests +module_nonansi_int2 normal,-g2005-sv ivltests module_nonansi_parray1 normal,-g2005-sv ivltests module_nonansi_parray2 normal,-g2005-sv ivltests module_nonansi_real1 normal,-g2005-sv ivltests diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index 539919c91..166463ba8 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -650,6 +650,10 @@ module3.12A normal ivltests main module3.12B normal ivltests module_inout_port_type CE ivltests module_input_port_type CE ivltests +module_nonansi_integer1 normal ivltests +module_nonansi_integer2 normal ivltests +module_nonansi_time1 normal ivltests +module_nonansi_time2 normal ivltests module_nonansi_vec1 normal ivltests module_nonansi_vec2 normal ivltests module_output_port_var1 normal ivltests diff --git a/ivtest/regress-vlog95.list b/ivtest/regress-vlog95.list index f5944b788..59207f27f 100644 --- a/ivtest/regress-vlog95.list +++ b/ivtest/regress-vlog95.list @@ -796,6 +796,8 @@ iuint1 normal,-g2009,-pallowsigned=1 ivltests logp2 normal,-g2009,-pallowsigned=1 ivltests mixed_width_case normal,-pallowsigned=1 ivltests mod_inst_pkg normal,-g2009,-pallowsigned=1 ivltests +module_nonansi_int1 normal,-g2005-sv,-pallowsigned=1 ivltests +module_nonansi_int2 normal,-g2005-sv,-pallowsigned=1 ivltests module_output_port_sv_var1 normal,-g2005-sv,-pallowsigned=1 ivltests module_output_port_sv_var2 normal,-g2005-sv,-pallowsigned=1 ivltests module_output_port_var1 normal,-pallowsigned=1 ivltests