diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc
index a19dc8610..eb96339e9 100644
--- a/tgt-vhdl/stmt.cc
+++ b/tgt-vhdl/stmt.cc
@@ -64,7 +64,6 @@ static int draw_stask_display(vhdl_process *proc, ivl_statement_t stmt)
          vhdl_expr *base = translate_expr(net);
          if (NULL == base)
             return 1;
-
          
          // Need to add a call to Type'Image for types not
          // supported by std.textio
diff --git a/tgt-vhdl/vhdl_element.cc b/tgt-vhdl/vhdl_element.cc
index 3deff1a69..2411be773 100644
--- a/tgt-vhdl/vhdl_element.cc
+++ b/tgt-vhdl/vhdl_element.cc
@@ -451,3 +451,10 @@ void vhdl_fcall::emit(std::ofstream &of, int level) const
    exprs_.emit(of, level);
 }
 
+void vhdl_nbassign_stmt::emit(std::ofstream &of, int level) const
+{
+   lhs_->emit(of, level);
+   of << " <= ";
+   rhs_->emit(of, level);
+   of << ";";
+}
diff --git a/tgt-vhdl/vhdl_element.hh b/tgt-vhdl/vhdl_element.hh
index e9788c7d2..0a44e9a6d 100644
--- a/tgt-vhdl/vhdl_element.hh
+++ b/tgt-vhdl/vhdl_element.hh
@@ -170,6 +170,21 @@ public:
 typedef std::list<vhdl_seq_stmt*> seq_stmt_list_t;
 
 
+/*
+ * Similar to Verilog non-blocking assignment, except the LHS
+ * must be a signal not a variable.
+ */
+class vhdl_nbassign_stmt : public vhdl_seq_stmt {
+public:
+   vhdl_nbassign_stmt(vhdl_var_ref *lhs, vhdl_expr *rhs)
+      : lhs_(lhs), rhs_(rhs) {}
+
+   void emit(std::ofstream &of, int level);
+private:
+   vhdl_var_ref *lhs_;
+   vhdl_expr *rhs_;
+};
+
 /*
  * Delay simulation indefinitely, until an event, or for a
  * specified time.