diff --git a/elab_expr.cc b/elab_expr.cc
index 508617b35..90c1937fc 100644
--- a/elab_expr.cc
+++ b/elab_expr.cc
@@ -1449,7 +1449,7 @@ NetExpr* PEIdent::elaborate_expr_net_part_(Design*des, NetScope*scope,
       }
 
 
-      if (net->sig()->sb_to_idx(msv) >= net->vector_width()) {
+      if (net->sig()->sb_to_idx(msv) >= (signed) net->vector_width()) {
 	    cerr << get_fileline() << ": error: part select ["
 		 << msv << ":" << lsv << "] out of range." << endl;
 	    des->errors += 1;
@@ -1558,7 +1558,8 @@ NetExpr* PEIdent::elaborate_expr_net_idx_do_(Design*des, NetScope*scope,
 	      // If the part select covers exactly the entire
 	      // vector, then do not bother with it. Return the
 	      // signal itself.
-	    if (net->sig()->sb_to_idx(lsv) == (wid-1) && wid == net->vector_width())
+	    if (net->sig()->sb_to_idx(lsv) == (signed) (wid-1) &&
+	        wid == net->vector_width())
 		  return net;
 
 	      // Otherwise, make a part select that covers the right range.
diff --git a/ivlpp/lexor.lex b/ivlpp/lexor.lex
index 1d24e698d..08bdc3f66 100644
--- a/ivlpp/lexor.lex
+++ b/ivlpp/lexor.lex
@@ -1471,6 +1471,7 @@ static void do_include()
         fprintf(yyout, "\n`line %u \"%s\" 1\n", istack->lineno+1, standby->path);
 
     standby->next = istack;
+    standby->stringify_flag = 0;
 
     istack->yybs = YY_CURRENT_BUFFER;
     istack = standby;
@@ -1710,6 +1711,7 @@ void reset_lexor(FILE* out, char* paths[])
     isp->str = 0;
     isp->ebs = 0;
     isp->lineno = 0;
+    isp->stringify_flag = 0;
 
     if (isp->file == 0)
     {
diff --git a/tgt-vvp/eval_expr.c b/tgt-vvp/eval_expr.c
index bca49cc0a..f7c5ed27d 100644
--- a/tgt-vvp/eval_expr.c
+++ b/tgt-vvp/eval_expr.c
@@ -1246,7 +1246,7 @@ static struct vector_info draw_binary_expr_arith(ivl_expr_t exp, unsigned wid)
       struct vector_info lv;
       struct vector_info rv;
 
-      const char*sign_string = ivl_expr_signed(exp)? "/s" : "";
+      const char*sign_string = ivl_expr_signed(le) && ivl_expr_signed(re)? "/s" : "";
 
       if ((ivl_expr_opcode(exp) == '+')
 	  && (ivl_expr_type(le) == IVL_EX_SIGNAL)
diff --git a/vvp/vpi_vthr_vector.cc b/vvp/vpi_vthr_vector.cc
index b58352978..72a043fe5 100644
--- a/vvp/vpi_vthr_vector.cc
+++ b/vvp/vpi_vthr_vector.cc
@@ -85,6 +85,9 @@ static int vthr_vec_get(int code, vpiHandle ref)
 	  case vpiSigned:
 	    return rfp->signed_flag;
 
+	  case vpiConstType:
+	    return vpiBinaryConst; // If this is a constant it is Binary.
+
 	  case vpiSize:
 	    return rfp->wid;