From d97c1bc6db6535a6601d12aabb6045f11049f757 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 29 Nov 2022 20:03:43 -0800 Subject: [PATCH 1/2] Insert drivers for undriven nets Trying to add a drive strength or delay to a undriven net will result in an assertion. Make sure that a driver is added to undriven nets. A driver is already added for all NetESignals, which covers most expression that can produce a raw net rvalue. But there are other ways we can end up with just a net as the rvalue, e.g. when applying a sign cast to a net. The following example triggers the issue ``` wire [7:0] a; wire [7:0] b = $signed(a); ``` Signed-off-by: Lars-Peter Clausen --- elaborate.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/elaborate.cc b/elaborate.cc index f23e796c4..8a9fb2514 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -185,7 +185,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const // expression. In this case, we will need to create a driver // (later) to carry strengths. bool need_driver_flag = false; - if (dynamic_cast(rval_expr)) + if (dynamic_cast(rval_expr) ||!rval->is_linked()) need_driver_flag = true; // expression elaboration should have caused the rval width to From 9e37f4382e32ee5970f87f8ed71d7c559caf0e50 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 29 Nov 2022 20:16:43 -0800 Subject: [PATCH 2/2] Add regression test for issue #793 Check that $signed/$unsigned works when being combinatorially assigned with a delay and the target of the function is a net without any drivers. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/br_gh793.v | 17 +++++++++++++++++ ivtest/regress-vlg.list | 1 + 2 files changed, 18 insertions(+) create mode 100644 ivtest/ivltests/br_gh793.v diff --git a/ivtest/ivltests/br_gh793.v b/ivtest/ivltests/br_gh793.v new file mode 100644 index 000000000..897064c00 --- /dev/null +++ b/ivtest/ivltests/br_gh793.v @@ -0,0 +1,17 @@ +// Check that $signed/$unsigned works when being combinatorially assigned with a +// delay and the target of the function is a net without any drivers. + +module top (); + wire [7:0] a; + wire signed [7:0] b; + assign #1 b = $signed(a); + + initial begin + #10 + if (b === 8'hzz) begin + $display("PASSED"); + end else begin + $display("FAILED"); + end + end +endmodule diff --git a/ivtest/regress-vlg.list b/ivtest/regress-vlg.list index df929e4c1..c6c70a513 100644 --- a/ivtest/regress-vlg.list +++ b/ivtest/regress-vlg.list @@ -349,6 +349,7 @@ br_gh632b normal,-S ivltests br_gh632c normal ivltests br_gh674 normal ivltests br_gh732 normal ivltests gold=br_gh732.gold +br_gh793 normal ivltests br_ml20150315 normal ivltests gold=br_ml_20150315.gold br_ml20150321 CE ivltests br_mw20171108 normal ivltests