From 2fc5f4f7d8bde155a59d8628f042cffc2e00db39 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Tue, 24 Jul 2007 16:12:40 -0700 Subject: [PATCH] Prepare for v0.8.5 release. Signed-off-by: Stephen Williams --- Makefile.in | 2 +- verilog.spec | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Makefile.in b/Makefile.in index de6139b08..707cafb3c 100644 --- a/Makefile.in +++ b/Makefile.in @@ -25,7 +25,7 @@ SHELL = /bin/sh # by the compiler. It reflects the assigned version number for the # product as a whole. Most components also print the CVS Name: token # in order to get a more automatic version stamp as well. -VERSION = 0.8.4 +VERSION = 0.8.5 prefix = @prefix@ exec_prefix = @exec_prefix@ diff --git a/verilog.spec b/verilog.spec index fd23df8fb..0845363ea 100644 --- a/verilog.spec +++ b/verilog.spec @@ -1,10 +1,10 @@ Summary: Icarus Verilog Name: verilog -Version: 0.8.4 +Version: 0.8.5 Release: 0 License: GPL Group: Applications/Engineering -Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.4.tar.gz +Source: ftp://icarus.com/pub/eda/verilog/v0.8/verilog-0.8.5.tar.gz URL: http://www.icarus.com/eda/verilog/index.html Packager: Stephen Williams @@ -29,7 +29,7 @@ engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. %prep -%setup -n verilog-0.8.4 +%setup -n verilog-0.8.5 %build %ifarch x86_64