diff --git a/elaborate.cc b/elaborate.cc
index 2b0fc6e25..c11b166d6 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -2515,9 +2515,9 @@ NetProc* PEventStatement::elaborate_st(Design*des, NetScope*scope,
 	    assert(enet);
 	     /* For synthesis we want just the inputs, but for the rest we
 	      * want inputs and outputs that may cause a value to change. */
-	    extern const char *target; /* Target backend from main.cc */
+	    extern bool synthesis; /* Synthesis flag from main.cc */
 	    bool rem_out = false;
-	    if (!strcmp(target, "fpga") || !strcmp(target, "pal")) {
+	    if (synthesis) {
 		  rem_out = true;
 	    }
 	    NexusSet*nset = enet->nex_input(rem_out);
diff --git a/main.cc b/main.cc
index a446bbda1..a4fe2d415 100644
--- a/main.cc
+++ b/main.cc
@@ -144,6 +144,11 @@ const bool CASE_SENSITIVE = false;
 const bool CASE_SENSITIVE = true;
 #endif
 
+/*
+ * Are we doing synthesis?
+ */
+bool synthesis = false;
+
 extern void cprop(Design*des);
 extern void synth(Design*des);
 extern void synth2(Design*des);
@@ -371,6 +376,9 @@ static void read_iconfig_file(const char*ipath)
 		  parm_to_flagmap(parm);
 
 	    } else if (strcmp(buf,"functor") == 0) {
+		if (strncmp(cp, "synth", 5) == 0) {
+		      synthesis = true;  // We are doing synthesis.
+		}
 		net_func tmp = name_to_net_func(cp);
 		if (tmp == 0) {
 		      cerr << "No such design transform function ``"