diff --git a/tgt-vhdl/vhdl_element.cc b/tgt-vhdl/vhdl_element.cc
index da7f961c4..5c0b343c9 100644
--- a/tgt-vhdl/vhdl_element.cc
+++ b/tgt-vhdl/vhdl_element.cc
@@ -244,3 +244,8 @@ void vhdl_wait_stmt::emit(std::ofstream &of, int level) const
    // TODO: There are lots of different types of `wait'
    of << "wait;";
 }
+
+void vhdl_scalar_type::emit(std::ofstream &of, int level) const
+{
+   of << name_;
+}
diff --git a/tgt-vhdl/vhdl_element.hh b/tgt-vhdl/vhdl_element.hh
index a03e5785f..f655ac106 100644
--- a/tgt-vhdl/vhdl_element.hh
+++ b/tgt-vhdl/vhdl_element.hh
@@ -45,6 +45,24 @@ private:
 
 typedef std::list<vhdl_element*> element_list_t; 
 
+class vhdl_type : public vhdl_element {
+public:
+   virtual ~vhdl_type() {}
+};
+
+/*
+ * A type at the moment is just a name. It shouldn't get
+ * too much more complex, as Verilog's type system is much
+ * simpler than VHDL's.
+ */
+class vhdl_scalar_type : public vhdl_element {
+public:
+   vhdl_scalar_type(const char *name) : name_(name) {}
+
+   void emit(std::ofstream &of, int level) const;
+private:
+   std::string name_;
+};
 
 /*
  * A concurrent statement appears in architecture bodies but not
@@ -117,6 +135,16 @@ private:
 };
 
 
+/*
+ * A variable declaration inside a process (although this isn't
+ * enforced here).
+ */
+class vhdl_var_decl : public vhdl_decl {
+public:
+   
+};
+
+
 /*
  * Instantiation of component. This is really only a placeholder
  * at the moment until the port mappings are worked out.