From c9e7aecf1d027589166e6c214c8a0a04158a8e70 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 1 Oct 2022 23:50:23 +0200 Subject: [PATCH 1/2] Implement `has_aa_term()` for cast expressions If the base expression of a cast expression has an automatic term then the cast expression itself has an automatic term. Make sure this is implemented so that an error is properly reported when using such an expression in a context where automatic variables are not allowed. Signed-off-by: Lars-Peter Clausen --- PExpr.cc | 15 +++++++++++++++ PExpr.h | 6 ++++++ 2 files changed, 21 insertions(+) diff --git a/PExpr.cc b/PExpr.cc index ff67da5e0..9038db959 100644 --- a/PExpr.cc +++ b/PExpr.cc @@ -142,6 +142,11 @@ PECastSize::~PECastSize() { } +bool PECastSize::has_aa_term(Design *des, NetScope *scope) const +{ + return base_->has_aa_term(des, scope); +} + PECastType::PECastType(data_type_t*t, PExpr*b) : target_(t), base_(b) { @@ -151,12 +156,22 @@ PECastType::~PECastType() { } +bool PECastType::has_aa_term(Design *des, NetScope *scope) const +{ + return base_->has_aa_term(des, scope); +} + PECastSign::PECastSign(bool signed_flag, PExpr *base) : base_(base) { signed_flag_ = signed_flag; } +bool PECastSign::has_aa_term(Design *des, NetScope *scope) const +{ + return base_->has_aa_term(des, scope); +} + PEBComp::PEBComp(char op, PExpr*l, PExpr*r) : PEBinary(op, l, r) { diff --git a/PExpr.h b/PExpr.h index f84e7d290..c765bec36 100644 --- a/PExpr.h +++ b/PExpr.h @@ -972,6 +972,8 @@ class PECastSize : public PExpr { unsigned expr_wid, unsigned flags) const; + virtual bool has_aa_term(Design *des, NetScope *scope) const; + virtual unsigned test_width(Design*des, NetScope*scope, width_mode_t&mode); @@ -997,6 +999,8 @@ class PECastType : public PExpr { virtual NetExpr*elaborate_expr(Design*des, NetScope*scope, unsigned expr_wid, unsigned flags) const; + virtual bool has_aa_term(Design *des, NetScope *scope) const; + virtual unsigned test_width(Design*des, NetScope*scope, width_mode_t&mode); @@ -1020,6 +1024,8 @@ class PECastSign : public PExpr { NetExpr* elaborate_expr(Design *des, NetScope *scope, unsigned expr_wid, unsigned flags) const; + virtual bool has_aa_term(Design *des, NetScope *scope) const; + unsigned test_width(Design *des, NetScope *scope, width_mode_t &mode); private: From c4397e66f9d4c48ef1c43b23b424ef98c2d060e1 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 2 Oct 2022 17:46:09 +0200 Subject: [PATCH 2/2] Add regression tests for automatic terms in cast expressions Check that a sign, width or type cast expression that contains an automatic term is detected as such and can not be used as the left-hand side in a procedural continuous assignment. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/automatic_error16.v | 21 +++++++++++++++++++++ ivtest/ivltests/automatic_error17.v | 22 ++++++++++++++++++++++ ivtest/ivltests/automatic_error18.v | 22 ++++++++++++++++++++++ ivtest/regress-sv.list | 3 +++ 4 files changed, 68 insertions(+) create mode 100644 ivtest/ivltests/automatic_error16.v create mode 100644 ivtest/ivltests/automatic_error17.v create mode 100644 ivtest/ivltests/automatic_error18.v diff --git a/ivtest/ivltests/automatic_error16.v b/ivtest/ivltests/automatic_error16.v new file mode 100644 index 000000000..5d844839a --- /dev/null +++ b/ivtest/ivltests/automatic_error16.v @@ -0,0 +1,21 @@ +// Check that an expression is correctly detected to contain an automatic +// variable if the variable is in a SystemVerilog size cast expression. + +module automatic_error; + + reg g; + + task automatic auto_task; + reg l; + + begin: block + assign g = 1'(l); + end + endtask + + initial begin + auto_task; + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/automatic_error17.v b/ivtest/ivltests/automatic_error17.v new file mode 100644 index 000000000..4615cefae --- /dev/null +++ b/ivtest/ivltests/automatic_error17.v @@ -0,0 +1,22 @@ +// Check that an expression is correctly detected to contain an automatic +// variable if the variable is in a SystemVerilog sign cast expression. + +module test; + + reg g; + + task automatic auto_task; + reg l; + + begin: block + assign g = signed'(l); + end + + endtask + + initial begin + auto_task; + $display("FAILED"); + end + +endmodule diff --git a/ivtest/ivltests/automatic_error18.v b/ivtest/ivltests/automatic_error18.v new file mode 100644 index 000000000..d6877158a --- /dev/null +++ b/ivtest/ivltests/automatic_error18.v @@ -0,0 +1,22 @@ +// Check that an expression is correctly detected to contain an automatic +// variable if the variable is in a SystemVerilog type cast expression. + +module test; + + reg g; + + task automatic auto_task; + reg l; + + begin: block + assign g = reg'(l); + end + + endtask + + initial begin + auto_task; + $display("FAILED"); + end + +endmodule diff --git a/ivtest/regress-sv.list b/ivtest/regress-sv.list index 4825b76a7..e9f4a5ad2 100644 --- a/ivtest/regress-sv.list +++ b/ivtest/regress-sv.list @@ -106,6 +106,9 @@ assign_op_real_array_oob normal,-g2009 ivltests assign_op_type normal,-g2009 ivltests automatic_error14 CE,-g2005-sv ivltests automatic_error15 CE,-g2005-sv ivltests +automatic_error16 CE,-g2005-sv ivltests +automatic_error17 CE,-g2005-sv ivltests +automatic_error18 CE,-g2005-sv ivltests bitp1 normal,-g2005-sv ivltests bits normal,-g2005-sv ivltests bits2 normal,-g2005-sv ivltests