diff --git a/PTask.cc b/PTask.cc
index 75e68bc22..034f38da6 100644
--- a/PTask.cc
+++ b/PTask.cc
@@ -41,7 +41,7 @@ void PTaskFunc::set_this(class_type_t*type, PWire*this_wire)
       assert(this_type_ == 0);
       this_type_ = type;
 
-	// Push a synthethis argument that is the "this" value.
+	// Push a synthesis argument that is the "this" value.
       if (ports_==0)
 	    ports_ = new vector<pform_tf_port_t>;
 
diff --git a/elab_expr.cc b/elab_expr.cc
index 8c53b6066..308e41606 100644
--- a/elab_expr.cc
+++ b/elab_expr.cc
@@ -1335,7 +1335,7 @@ unsigned PECallFunction::test_width_method_(Design*des, NetScope*scope,
       if (net == 0)
 	    return 0;
 
-	// Look fonr built in string attributes.
+	// Look for built in string attributes.
       if (net->data_type()==IVL_VT_STRING) {
 
 	    if (method_name == "len") {
@@ -3843,7 +3843,7 @@ NetExpr* PEIdent::elaborate_expr(Design*des, NetScope*scope,
       }
 
 	// Maybe this is a method attached to an enumeration name? If
-	// this is system verilog, then test to see if the name is
+	// this is SystemVerilog, then test to see if the name is
 	// really a method attached to an object.
       if (gn_system_verilog() && found_in==0 && path_.size() >= 2) {
 	    pform_name_t use_path = path_;
diff --git a/elaborate.cc b/elaborate.cc
index 1693b3215..974312c9e 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -1581,7 +1581,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 
 		    // Special case: If the output port is an unpacked
 		    // array, then there should be no sub-ports and
-		    // the passed pexxpression is processed
+		    // the passed port expression is processed
 		    // differently. Note that we are calling it the
 		    // "r-value" expression, but since this is an
 		    // output port, we assign to it from the internal object.
diff --git a/ivl_target.h b/ivl_target.h
index 0198eec09..4cb84d786 100644
--- a/ivl_target.h
+++ b/ivl_target.h
@@ -300,7 +300,7 @@ typedef enum ivl_lpm_type_e {
       IVL_LPM_CONCAT = 16,
       IVL_LPM_CONCATZ = 36, /* Transparent concat */
       IVL_LPM_CMP_EEQ= 18, /* Case EQ (===) */
-      IVL_LPM_CMP_EQX= 37, /* Windcard EQ (==?) */
+      IVL_LPM_CMP_EQX= 37, /* Wildcard EQ (==?) */
       IVL_LPM_CMP_EQZ= 38, /* casez EQ */
       IVL_LPM_CMP_EQ = 10,
       IVL_LPM_CMP_GE =  1,
@@ -1285,8 +1285,8 @@ extern unsigned    ivl_lpm_lineno(ivl_lpm_t net);
  * magnitude compare, the signedness does matter. In any case, the
  * result of the compare is always unsigned.
  *
- * The EQX and EQZ nodes are windcard compares, where xz bits (EQX) or
- * z bits (EQZ) in the data(1) operand are treated as windcards. no
+ * The EQX and EQZ nodes are wildcard compares, where xz bits (EQX) or
+ * z bits (EQZ) in the data(1) operand are treated as wildcards. no
  * bits in the data(0) operand are wild. This matches the
  * SystemVerilog convention for the ==? operator.
  *
diff --git a/libveriuser/getsimtime.c b/libveriuser/getsimtime.c
index 0a7ad914f..a8812bd0c 100644
--- a/libveriuser/getsimtime.c
+++ b/libveriuser/getsimtime.c
@@ -115,7 +115,7 @@ PLI_INT32 tf_getlongtime(PLI_INT32 *high)
 }
 
 /*
- * This function is not defined in the IEE standard, but is provided for
+ * This function is not defined in the IEEE standard, but is provided for
  * compatibility with other simulators. On platforms that support this,
  * make it a weak symbol just in case the user has defined their own
  * function for this.
diff --git a/netlist.h b/netlist.h
index 28dc78667..c0ccecbc8 100644
--- a/netlist.h
+++ b/netlist.h
@@ -765,7 +765,7 @@ class NetNet  : public NetObj, public PortType {
       unsigned peek_eref() const;
 
 	// Assignment statements count their lrefs here. And by
-	// asignment statements, we mean BEHAVIORAL assignments.
+	// assignment statements, we mean BEHAVIORAL assignments.
       void incr_lref();
       void decr_lref();
       unsigned peek_lref() const { return lref_count_; }
@@ -2216,7 +2216,7 @@ class NetPartSelect  : public NetNode {
  *
  *      wire [7:0] foo = NetSubstitute(bar, bat, off);
  *
- * meaus that bar is a vector the same width as foo, bat is a narrower
+ * means that bar is a vector the same width as foo, bat is a narrower
  * vector. The off is a constant offset into the bar vector. This
  * looks something like this:
  *
@@ -2287,7 +2287,7 @@ class NetBUFZ  : public NetNode {
  *
  *     0   -- Output (always returns 0 or 1)
  *     1   -- Input
- *     2   -- Input (windcard input for EQX and EQZ variants)
+ *     2   -- Input (wildcard input for EQX and EQZ variants)
  */
 class NetCaseCmp  : public NetNode {
 
diff --git a/netmisc.cc b/netmisc.cc
index e345cb977..26d523d3c 100644
--- a/netmisc.cc
+++ b/netmisc.cc
@@ -893,7 +893,7 @@ static NetExpr* do_elab_and_eval(Design*des, NetScope*scope, PExpr*pe,
             }
       }
 
-	// If the context_width sent is is actually the minimim width,
+	// If the context_width sent is is actually the minimum width,
 	// then raise the context_width to be big enough for the
 	// lossless expression.
       if (force_expand && context_width > 0) {
diff --git a/nettypes.cc b/nettypes.cc
index 4a01d4d8a..2f2e3988f 100644
--- a/nettypes.cc
+++ b/nettypes.cc
@@ -141,7 +141,7 @@ bool prefix_to_slice(const std::vector<netrange_t>&dims,
 
 	// Now similarly go through the prefix numbers, working
 	// through the dimensions until we run out. Accumulate a
-	// growing slice width (acc_wid) that is used to caculate the
+	// growing slice width (acc_wid) that is used to calculate the
 	// growing offset (acc_off).
       list<long>::const_iterator icur = prefix.end();
       do {
diff --git a/pform_types.h b/pform_types.h
index de616f1d9..149ae9f27 100644
--- a/pform_types.h
+++ b/pform_types.h
@@ -50,7 +50,7 @@ typedef named<verinum> named_number_t;
 typedef named<PExpr*> named_pexpr_t;
 
 /*
- * The pform_range_t holds variable diimensions for type
+ * The pform_range_t holds variable dimensions for type
  * declarations. The two expressions are interpreted as the first and
  * last values of the range. For example:
  *
diff --git a/synth2.cc b/synth2.cc
index e0a964f04..2f8bf7fb2 100644
--- a/synth2.cc
+++ b/synth2.cc
@@ -808,8 +808,8 @@ bool NetCase::synth_async_casez_(Design*des, NetScope*scope,
 						   sel_width, case_kind);
 	    des->add_node(condit_dev);
 	    condit_dev->set_line(*this);
-	      // Note that the expression that may have windcards must
-	      // go in the pin(2) input. This is the definiton of the
+	      // Note that the expression that may have wildcards must
+	      // go in the pin(2) input. This is the definition of the
 	      // NetCaseCmp statement.
 	    connect(condit_dev->pin(1), esig->pin(0));
 	    connect(condit_dev->pin(2), guard->pin(0));
diff --git a/tgt-vlog95/vlog95.c b/tgt-vlog95/vlog95.c
index 1765b9468..861cff554 100644
--- a/tgt-vlog95/vlog95.c
+++ b/tgt-vlog95/vlog95.c
@@ -208,7 +208,7 @@ int target_design(ivl_design_t des)
 	    assert(indent == 0);
 	    fprintf(vlog_out, "endmodule /* ivl_root_scope */\n");
       }
-	/* Emit the rest of the scope objets. */
+	/* Emit the rest of the scope objects. */
       for (idx = 0; idx < nroots; idx += 1) emit_scope(roots[idx], 0);
 
       free_emitted_scope_list();
diff --git a/tgt-vvp/eval_vec4.c b/tgt-vvp/eval_vec4.c
index e38f7238a..9030cc06c 100644
--- a/tgt-vvp/eval_vec4.c
+++ b/tgt-vvp/eval_vec4.c
@@ -415,7 +415,7 @@ static void draw_binary_vec4_land(ivl_expr_t expr)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
 	/* Now push the right expression. Again, reduce to a single
-	   bit if necessasry. */
+	   bit if necessary. */
       draw_eval_vec4(re);
       if (ivl_expr_width(re) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
@@ -615,7 +615,7 @@ static void draw_binary_vec4_lor(ivl_expr_t expr)
 	    fprintf(vvp_out, "    %%or/r;\n");
 
 	/* Now push the right expression. Again, reduce to a single
-	   bit if necessasry. */
+	   bit if necessary. */
       draw_eval_vec4(re);
       if (ivl_expr_width(re) > 1)
 	    fprintf(vvp_out, "    %%or/r;\n");
@@ -952,7 +952,7 @@ static void draw_select_pad_vec4(ivl_expr_t expr)
 }
 
 /*
- * This function handles the speical case of a call to the internal
+ * This function handles the special case of a call to the internal
  * functions $ivl_darray_method$pop_back et al. The first (and only)
  * argument is the signal that represents a dynamic queue. Generate a
  * %qpop instruction to pop a value and push it to the vec4 stack.
diff --git a/tgt-vvp/vvp_priv.h b/tgt-vvp/vvp_priv.h
index e23916e03..5255058cc 100644
--- a/tgt-vvp/vvp_priv.h
+++ b/tgt-vvp/vvp_priv.h
@@ -237,13 +237,13 @@ extern void draw_eval_real(ivl_expr_t ex);
 extern int draw_eval_bool64(ivl_expr_t ex);
 
 /*
- * The draw_eval_string functio evaluates the expression as a string,
+ * The draw_eval_string function evaluates the expression as a string,
  * and pushes the string onto the string stack.
  */
 extern void draw_eval_string(ivl_expr_t ex);
 
 /*
- * The draw_eval_string functio evaluates the expression as an object,
+ * The draw_eval_string function evaluates the expression as an object,
  * and pushes the object onto the object stack.
  */
 extern int draw_eval_object(ivl_expr_t ex);
diff --git a/tgt-vvp/vvp_process.c b/tgt-vvp/vvp_process.c
index 3980b9575..571c8b100 100644
--- a/tgt-vvp/vvp_process.c
+++ b/tgt-vvp/vvp_process.c
@@ -671,7 +671,7 @@ static int show_stmt_case(ivl_statement_t net, ivl_scope_t sscope)
 
 	      /* Duplicate the case expression so that the cmp
 		 instructions below do not completely erase the
-		 value. Do this in fromt of each compare. */
+		 value. Do this in front of each compare. */
 	    fprintf(vvp_out, "    %%dup/vec4;\n");
 	    draw_eval_vec4(cex);
 
@@ -767,7 +767,7 @@ static int show_stmt_case_r(ivl_statement_t net, ivl_scope_t sscope)
 		  continue;
 	    }
 
-	      /* The referene value... */
+	      /* The reference value... */
 	    fprintf(vvp_out, "    %%dup/real;\n");
 	      /* The guard value... */
 	    draw_eval_real(cex);
@@ -2321,7 +2321,7 @@ int draw_process(ivl_process_t net, void*x)
       fprintf(vvp_out, "    .scope S_%p;\n", scope);
 
 	/* Generate the entry label. Just give the thread a number so
-	   that we ar certain the label is unique. */
+	   that we are certain the label is unique. */
       fprintf(vvp_out, "T_%u ;\n", thread_count);
 
 	/* Draw the contents of the thread. */
diff --git a/vhdlpp/parse.y b/vhdlpp/parse.y
index 0927022be..c3a4e2ab9 100644
--- a/vhdlpp/parse.y
+++ b/vhdlpp/parse.y
@@ -753,7 +753,7 @@ composite_type_definition
 
   /* The when...else..when...else syntax is not a general expression
      in VHDL but a specific sort of assignment statement model. We
-     create Exppression objects for it, but the parser will only
+     create Expression objects for it, but the parser will only
      recognize it it in specific situations. */
 concurrent_conditional_signal_assignment /* IEEE 1076-2008 P11.6 */
   : name LEQ waveform K_when expression else_when_waveforms ';'
diff --git a/vpi/sys_darray.c b/vpi/sys_darray.c
index 507bb974a..7fe90f4f4 100644
--- a/vpi/sys_darray.c
+++ b/vpi/sys_darray.c
@@ -263,7 +263,7 @@ static PLI_INT32 to_vec_calltf(ICARUS_VPI_CONST PLI_BYTE8*name)
 			                                 offset));
 			      vec_ptr->bval |= (bval >> (darr_word_size -
 			                                 offset));
-			  /* Start at the begining of the next vector part. */
+			  /* Start at the beginning of the next vector part. */
 			} else {
 			      offset = 0;
 			}
diff --git a/vpi/table_mod.c b/vpi/table_mod.c
index 43609989b..c8157fdda 100644
--- a/vpi/table_mod.c
+++ b/vpi/table_mod.c
@@ -629,7 +629,7 @@ static unsigned initialize_table_model(vpiHandle callh, const char *name,
 }
 
 /*
- * Routine to evalute the table model using the current input values.
+ * Routine to evaluate the table model using the current input values.
  */
 static double eval_table_model(vpiHandle callh, p_table_mod table)
 {
diff --git a/vvp/compile.cc b/vvp/compile.cc
index eb74b8be4..3bf1d7474 100644
--- a/vvp/compile.cc
+++ b/vvp/compile.cc
@@ -1962,7 +1962,7 @@ void compile_param_string(char*label, char*name, char*value,
                           bool local_flag,
                           long file_idx, long lineno)
 {
-	// name and value become owned bi vpip_make_string_param
+	// name and value become owned by vpip_make_string_param
       vpiHandle obj = vpip_make_string_param(name, value, local_flag, file_idx, lineno);
       compile_vpi_symbol(label, obj);
       vpip_attach_to_current_scope(obj);
diff --git a/vvp/compile.h b/vvp/compile.h
index 60e094cb8..bfe20cd52 100644
--- a/vvp/compile.h
+++ b/vvp/compile.h
@@ -512,7 +512,7 @@ extern void compile_port_info( unsigned index, int vpi_port_type, unsigned width
  * given name.
  *
  * The vpi_type_code argument of compile_net() is one of the vpi
- * object codes for the equivelent variable types. The supported codes
+ * object codes for the equivalent variable types. The supported codes
  * are:
  *   vpiLogic  -- 4-value logic
  *   vpiIntVar -- 2-value logic
diff --git a/vvp/dff.cc b/vvp/dff.cc
index ed177373f..0070c5fcc 100644
--- a/vvp/dff.cc
+++ b/vvp/dff.cc
@@ -71,7 +71,7 @@ void vvp_dff::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
 }
 
 /*
- * The recv_clear and recv_set function respond to asynchronout
+ * The recv_clear and recv_set function respond to asynchronous
  * clear/set input by propagating the desired output.
  *
  * NOTE: Don't touch the d_ value, because that tracks the D input,
diff --git a/vvp/resolv.cc b/vvp/resolv.cc
index 4aef59ef5..cd6bfa9e6 100644
--- a/vvp/resolv.cc
+++ b/vvp/resolv.cc
@@ -29,7 +29,7 @@
 /*
  * The core functor for a resolver node stores all the input values
  * received by that node. This provides the necessary information
- * for implementing the $countdrivers system call. For efficency,
+ * for implementing the $countdrivers system call. For efficiency,
  * the resolver is implemented using a balanced quaternary tree, so
  * the core functor also stores the current value for each branch
  * of the tree, to eliminate the need to re-evaluate branches whose
diff --git a/vvp/vpi_signal.cc b/vvp/vpi_signal.cc
index 8750c3a65..552fb499f 100644
--- a/vvp/vpi_signal.cc
+++ b/vvp/vpi_signal.cc
@@ -136,7 +136,7 @@ static vpiHandle fill_in_net4(struct __vpiSignal*obj,
 			      bool signed_flag, vvp_net_t*node);
 
 /*
- * The standard formating/conversion routines.
+ * The standard formatting/conversion routines.
  * They work with full or partial signals.
  */
 
diff --git a/vvp/vthread.cc b/vvp/vthread.cc
index 21eef0b28..39c463fc5 100644
--- a/vvp/vthread.cc
+++ b/vvp/vthread.cc
@@ -949,7 +949,7 @@ bool of_ASSIGN_VEC4_A_D(vthread_t thr, vvp_code_t cp)
       unsigned wid = val.size();
       const unsigned array_wid = cp->array->get_word_size();
 
-	// Abort if flags[4] is set. This can happen if the calulation
+	// Abort if flags[4] is set. This can happen if the calculation
 	// into an index register failed.
       if (thr->flags[4] == BIT4_1)
 	    return true;
@@ -992,7 +992,7 @@ bool of_ASSIGN_VEC4_A_E(vthread_t thr, vvp_code_t cp)
       unsigned wid = val.size();
       const unsigned array_wid = cp->array->get_word_size();
 
-	// Abort if flags[4] is set. This can happen if the calulation
+	// Abort if flags[4] is set. This can happen if the calculation
 	// into an index register failed.
       if (thr->flags[4] == BIT4_1)
 	    return true;
@@ -1038,7 +1038,7 @@ bool of_ASSIGN_VEC4_OFF_D(vthread_t thr, vvp_code_t cp)
       int off = thr->words[off_index].w_int;
       vvp_time64_t del = thr->words[del_index].w_uint;
 
-	// Abort if flags[4] is set. This can happen if the calulation
+	// Abort if flags[4] is set. This can happen if the calculation
 	// into an index register failed.
       if (thr->flags[4] == BIT4_1)
 	    return true;
@@ -1080,7 +1080,7 @@ bool of_ASSIGN_VEC4_OFF_E(vthread_t thr, vvp_code_t cp)
 
       int off = thr->words[off_index].w_int;
 
-	// Abort if flags[4] is set. This can happen if the calulation
+	// Abort if flags[4] is set. This can happen if the calculation
 	// into an index register failed.
       if (thr->flags[4] == BIT4_1)
 	    return true;